XC61C
Series
Low Voltage Detectors (V
DF
= 0.8V½1.5V)
Standard Voltage Detectors (V
DF
1.6V½6.0V)
ETR0201_006
■GENERAL
DESCRIPTION
The XC61C series are highly precise, low power consumption voltage detectors, manufactured using CMOS and laser
trimming technologies.
Detect voltage is extremely accurate with minimal temperature drift.
Both CMOS and N-channel open drain output configurations are available.
■APPLICATIONS
●Microprocessor
reset circuitry
●Memory
battery back-up circuits
●Power-on
reset circuits
●Power
failure detection
●System
battery life and charge voltage monitors
■FEATURES
Highly Accurate
: ± 2%
(Low Voltage VD: 0.8V~1.5V)
(Standard Voltage VD: 1.6V~6.0V)
± 1%
(Standard Voltage VD: 2.6V~5.0V)
Low Power Consumption
: 0.7μA (TYP.) [V
IN
=1.5V]
Detect Voltage Range
: 0.8V ~ 6.0V in 100mV increments
Operating Voltage Range
: 0.7V ~ 6.0V (Low Voltage)
0.7V½10.0V (Standard Voltage)
Detect Voltage Temperature Characteristics
:
±100ppm/℃
(TYP.) @Ta=25
O
C
Output Configuration
: N-channel open drain or CMOS
CMOS
Ultra Small Packages
: SSOT-24 (150mW)
SOT-23 (250mW)
SOT-89 (500mW)
TO-92 (300mW)
■TYPICAL
APPLICATION CIRCUITS
■TYPICAL
PERFORMANCE CHARACTERISTICS
1/17
XC61C
Series
■PIN
CONFIGURATION
■PIN
ASSIGNMENT
PIN NUMBER
SSOT-24
2
4
1
3
SOT-23
3
2
1
-
SOT-89
2
3
1
-
TO-92 (T)
TO-92 (L)
PIN NAME
V
IN
V
SS
V
OUT
NC
FUNCTION
Supply Voltage
t
I
t
Ground
Output
No Connection
2
3
1
-
1
2
3
-
■PRODUCT
CLASSIFICATION
●Ordering
Information
XC61C①②③④⑤⑥⑦
DESIGNATOR
①
② ③
④
⑤
DESCRIPTION
Output Configuration
Detect Voltage
Output Delay
Detect Accuracy
SYMBOL
C
N
08 ~ 60
0
1
2
N
M
P
T
L
R
L
H
B
DESCRIPTION
: CMOS output
: N-ch open drain output
: e.g.0.9V
→ ②0, ③9
: e.g.1.5V
→ ②1, ③5
: No delay
: Within
±1%
: Within
±2%
: SSOT-24 (SC-82)
: SOT-23
: SOT-89
: TO-92 (Standard)
: TO-92 (Custom pin configuration)
: Embossed tape, standard feed
: Embossed tape, reverse feed
: Paper type (TO-92)
: Bag (TO-92)
⑥
Package
⑦
Device Orientation
2/17
XC61C
Series
■BLOCK
DIAGRAMS
(1) CMOS Output
(2) N-ch Open Drain Output
■ABSOLUTE
MAXIMUM RATINGS
Ta = 25
O
C
PARAMETER
Input Voltage
Output Current
CMOS
Output Voltage
N-ch Open Drain Output *1
N-ch Open Drain Output *2
SSOT-24
Power Dissipation
SOT-23
SOT-89
TO-92
Operating Temperature Range
Storage Temperature Range
Pd
V
OUT
*1
*2
SYMBOL
V
IN
I
OUT
RATINGS
9.0
12.0
50
V
SS
-0.3 ~ V
IN
+0.3
V
SS
-0.3 ~ 9.0
V
SS
-0.3 ~ 12.0
150
250
500
300
-40½+85
-40½+125
mW
V
UNITS
V
mA
Topr
Tstg
O
O
C
C
*1: Low voltage: V
DF(T)
=0.8V~1.5V
*2: Standard voltage: V
DF(T)
=1.6V~6.0V
3/17
XC61C
Series
■ELECTRICAL
CHARACTERISTICS
V
DF (T)
= 0.8V to 6.0V ± 2%
V
DF (T)
= 2.6V to 5.0V ± 1%
PARAMETER
Detect Voltage
SYMBOL
V
DF
MIN.
V
DF(T)
x 0.98
V
DF(T)
V
DF(T)
=2.6V~5.0V *2
x 0.99
V
DF
x 0.02
V
IN
= 1.5V
-
V
IN
= 2.0V
-
V
IN
= 3.0V
-
V
IN
= 4.0V
-
V
IN
= 5.0V
-
V
DF(T)
= 0.8V to 1.5V
0.7
0.7
V
DF(T)
= 1.6V to 6.0V
0.10
V
IN
= 0.7V
N-ch V
DS
= 0.5V
V
IN
= 1.0V
0.85
CMOS, P-ch V
DS
= 2.1V
V
IN
= 6.0V
-
1.0
V
IN
= 1.0V
V
IN
= 2.0V
3.0
N-ch V
DS
= 0.5V
V
IN
= 3.0V
5.0
V
IN
= 4.0V
6.0
V
IN
= 5.0V
7.0
CMOS, P-ch V
DS
= 2.1V
V
IN
= 8.0V
-
V
IN
=6.0V, V
OUT
=6.0V*1
CMOS
-
V
IN
=10.0V, V
OUT
=10.0V*2
N-ch Open Drain
-
-40℃
≦
Topr
≦
85℃
Inverts from V
DR
to V
OUT
-
-
CONDITIONS
V
DF(T)
=0.8V~1.5V *1
V
DF(T)
=1.6V~6.0V *2
TYP.
V
DF(T)
V
DF(T)
V
DF
x 0.05
0.7
0.8
0.9
1.0
1.1
-
-
0.80
2.70
-7.5
2.2
7.7
10.1
11.5
13.0
-10.0
10
10
±100
0.03
MAX.
V
DF(T)
x 1.02
V
DF(T)
x 1.01
V
DF
x 0.08
2.3
2.7
3.0
3.2
3.6
6.0
10.0
-
-
-1.5
-
-
-
-
-
-2.0
-
100
-
0.20
Ta=25℃
UNITS
CIRCUITS
V
V
V
1
1
1
Hysteresis Range
V
HYS
Supply Current
I
SS
μA
2
Operating Voltage *1
Operating Voltage *2
Output Current *1
V
IN
V
1
3
4
I
OUT
Output Current *2
mA
3
4
nA
ppm/
℃
ms
3
-
5
Leak Current
I
leak
Temperature
ΔV
DF
Characteristics
ΔTopr½V
DF
Delay Time
tDLY
(V
DR
→V
OUT
inversion)
NOTE:
*1: Low Voltage: V
DF(T)
=0.8V~1.5V
*2: Standard Voltage: V
DF(T)
=1.6V~6.0V
V
DF (T)
: Setting detect voltage
Release Voltage: V
DR
= V
DF
+ V
HYS
4/17
XC61C
Series
■OPERATIONAL
EXPLANATION
(Especially prepared for CMOS output products)
①
When input voltage (V
IN
) rises above detect voltage (V
DF
), output voltage (V
OUT
) will be equal to V
IN
.
(A condition of high impedance exists with N-ch open drain output configurations.)
②
When input voltage (V
IN
) falls below detect voltage (V
DF
), output voltage (V
OUT
) will be equal to the ground voltage
(V
SS
) level.
③
When input voltage (V
IN
) falls to a level below that of the minimum operating voltage (V
MIN
), output will become
unstable. In this condition, V
IN
will equal the pulled-up output (should output be pulled-up.)
④
When input voltage (V
IN
) rises above the ground voltage (V
SS
) level, output will be unstable at levels below the
minimum operating voltage (V
MIN
). Between the V
MIN
and detect release voltage (V
DR
) levels, the ground voltage (V
SS
)
level will be maintained.
⑤
When input voltage (V
IN
) rises above detect release voltage (V
DR
), output voltage (V
OUT
) will be equal to V
IN
.
(A condition of high impedance exists with N-ch open drain output configurations.)
⑥
The difference between V
DR
and V
DF
represents the hysteresis range.
●Timing
Chart
5/17
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
