100336 Low Power 4-Stage Counter/Shift Register
August 1989
Revised August 2000
100336
Low Power 4-Stage Counter/Shift Register
General Description
The 100336 operates as either a modulo-16 up/down
counter or as a 4-bit bidirectional shift register. Three
Select (S
n
) inputs determine the mode of operation, as
shown in the Function Select table. Two Count Enable
(CEP, CET) inputs are provided for ease of cascading in
multistage counters. One Count Enable (CET) input also
doubles as a Serial Data (D
0
) input for shift-up operation.
For shift-down operation, D
3
is the Serial Data input. In
counting operations the Terminal Count (TC) output goes
LOW when the counter reaches 15 in the count/up mode or
0 (zero) in the count/down mode. In the shift modes, the TC
output repeats the Q
3
output. The dual nature of this TC/Q
3
output and the D
0
/CET input means that one interconnec-
tion from one stage to the next higher stage serves as the
link for multistage counting or shift-up operation. The indi-
vidual Preset (P
n
) inputs are used to enter data in parallel
or to preset the counter in programmable counter applica-
tions. A HIGH signal on the Master Reset (MR) input over-
rides all other inputs and asynchronously clears the flip-
flops. In addition, a synchronous clear is provided, as well
as a complement function which synchronously inverts the
contents of the flip-flops. All inputs have 50 k
Ω
pull-down
resistors.
Features
s
40% power reduction of the 100136
s
2000V ESD protection
s
Pin/function compatible with 100136
s
Voltage compensated operating range
= −
4.2V to
−
5.7V
s
Available to industrial grade temperature range
Ordering Code:
Order Number
100336SC
100336PC
100336QC
100336QI
Package Number
M24B
N24E
V28A
V28A
Package Description
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (
−
40
°
C to
+
85
°
C)
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
24-Pin DIP/SOIC
28-Pin PLCC
Logic Symbol
© 2000 Fairchild Semiconductor Corporation
DS010584
www.fairchildsemi.com
100336
Function Select Table
S
2
L
L
L
L
H
H
H
H
S
1
L
L
H
H
L
L
H
H
S
0
L
H
L
H
L
H
L
H
Function
Parallel Load
Complement
Shift Left
Shift Right
Count Down
Clear
Count Up
Hold
Pin Descriptions
Pin Names
CP
CEP
D
0
/CET
S
0
–S
2
MR
P
0
–P
3
D
3
TC
Q
0
–Q
3
Q
0
–Q
3
Description
Clock Pulse Input
Count Enable Parallel Input (Active LOW)
Serial Data Input/Count Enable
Trickle Input (Active LOW)
Select Inputs
Master Reset Input
Preset Inputs
Serial Data Input
Terminal Count Output
Data Outputs
Complementary Data Outputs
Truth Table
Q
0
=
LSB
Inputs
Outputs
MR S
2
S
1
S
0
CEP D
0
/CET D
3
CP Q
3
Q
2
Q
1
Q
0
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
L
L
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
L
L
H
H
L
H
L
H
L
L
L
H
L
L
L
H
L
H
L
H
L
L
H
L
H
X
X
X
X
L
H
X
X
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
H
X
L
L
H
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
TC
L
L
D
3
1
1
H
H
2
2
H
H
L
L
L
L
L
H
H
H
H
Mode
Preset (Parallel Load)
Invert
Shift to LSB
Count Down
Count Down with CEP not active
Count Down with CET not active
Clear
Count Up
Count Up with CEP not active
Count Up with CET not active
Hold
P
3
P
2
P
1
P
0
Q
3
Q
2
Q
1
Q
0
D
3
Q
3
Q
2
Q
1
(Q
0–3
) minus 1
Q
2
Q
1
Q
0
D
0
Q
3
(Note 1) Shift to MSB
X Q
3
Q
2
Q
1
Q
0
X Q
3
Q
2
Q
1
Q
0
L
L
L
L
(Q
0–3
) plus 1
X Q
3
Q
2
Q
1
Q
0
X Q
3
Q
2
Q
1
Q
0
X Q
3
Q
2
Q
1
Q
0
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Asynchronous
Master Reset
1
=
L if Q
0
–Q
3
=
LLLL
H if Q
0
–Q
3
≠
LLLL
2
=
L if Q
0
–Q
3
=
HHHH
H if Q
0
–Q
3
≠
HHHH
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Don't Care
=
LOW-to-HIGH Transition
Note 1:
Before the clock, TC is Q
3
After the clock, TC is Q
2
www.fairchildsemi.com
2
100336
Absolute Maximum Ratings
(Note 2)
Storage Temperature (T
STG
)
Maximum Junction Temperature (T
J
)
V
EE
Pin Potential to Ground Pin
Input Voltage (DC)
Output Current (DC Output HIGH)
ESD (Note 3)
−
65
°
C to
+
150
°
C
+
150
°
C
−
7.0V to
+
0.5V
V
EE
to
+
0.5V
Recommended Operating
Conditions
Case Temperature (T
C
)
Commercial
Industrial
Supply Voltage (V
EE
)
0
°
C to
+
85
°
C
−
40
°
C to
+
85
°
C
−
5.7V to
−
4.2V
−
50 mA
≥
2000V
Note 2:
Absolute maximum ratings are those values beyond which the
device may be damaged or have its useful life impaired. Functional opera-
tion under these conditions is not implied.
Note 3:
ESD testing conforms to MIL-STD-883, Method 3015.
Commercial Version
DC Electrical Characteristics
(Note 4)
V
EE
= −
4.2V to
−
5.7V, V
CC
=
V
CCA
=
GND, T
C
=
0°C to
+85°C
Symbol
Parameter
Min
Typ
V
OH
V
OL
V
OHC
V
OLC
V
IH
V
IL
I
IL
I
IH
I
EE
Output HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input LOW Current
Input HIGH Current
Power Supply Current
−165
−1165
−1830
0.50
240
−80
−1025
−1830
−1035
−1610
−870
−1475
−955
−1705
Max
−870
−1620
Units
mV
mV
mV
mV
mV
mV
µA
µA
V
IN
=V
IH (Max)
or V
IL (Min)
V
IN
=
V
IH(Min)
or V
IL (Max)
Guaranteed HIGH Signal
for All Inputs
Guaranteed LOW Signal
for All Inputs
V
IN
=
V
IL
(Min)
V
IN
=
V
IH
(Max)
Inputs Open
Conditions
Loading with
50Ω to
−2.0V
Loading with
50Ω to
−2.0V
Note 4:
The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are cho-
sen to guarantee operation under “worst case” conditions.
www.fairchildsemi.com
4
单片机
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
