ADVANCE INFORMATION DATASHEET
LOW POWER PCIE GEN2/3 & QPI CLOCK FOR INTEL-BASED SERVERS
932SQL420
General Description
The 932SQL420 is a low power version of the CK420BQ
synthesizer for Intel-based server platforms. The
932SQL420 is driven with a 25MHz crystal for maximum
performance. It generates CPU outputs of 100Mhz. This
device has a "low-drift" non-spread SAS/SRC PLL for use
in systems that need to communicate across PCIe
domains.
Features/Benefits
•
0.5% down spread capable on CPU, SRC and PCI
•
•
outputs; reduce EMI
Additional down spread amounts selectable via SMBus;
maximal system flexibility
64-pin TSSOP and MLF packages; space savings
Output Features
•
4 - Low-Power HCSL-compatible (LP-HCSL) CPU
•
•
•
•
•
•
•
outputs
2 - LP-HCSL NS_SAS outputs
2 - LP-HCSL NS_SRC outputs
3 - LP-HCSL SRC outputs
1 - LP-HCSL DOT96 output
1 - 3.3V 48M output
5 - 3.3V PCI outputs
1 - 3.3V 14.318M output
Recommended Application
Low Power CK420BQ
Key Specifications
•
CPU, SRC, NS_SRC and NS_SAS cycle-cycle jitter
•
•
•
•
<50ps
Output to output skew <50ps
Phase jitter: PCIe Gen2 <2.7ps rms
Phase jitter: QPI <0.3ps rms
Phase jitter: NS-SAS <1.3ps rms using long period
phase jitter method
PIn Configurations
SMBCLK
GND14
AVDD14
VDD14
v
REF14_3x/TEST_SEL
GND14
GNDXTAL
X1_25
X2_25
VDDXTAL
GNDPCI
VDDPCI
PCI4_2x
PCI3_2x
PCI2_2x
PCI1_2x
PCI0_2x
GNDPCI
VDDPCI
VDD48
48M_2x
GND48
GND96
DOT96_LPT
DOT96_LPC
AVDD96
TEST_MODE
CKPWRGD#/PD
VDDSRC
SRC0_LPT
SRC0_LPC
GNDSRC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SMBDAT
VDDCPU
CPU3_LPT
CPU3_LPC
CPU2_LPT
CPU2_LPC
GNDCPU
VDDCPU
CPU1_LPT
CPU1_LPC
CPU0_LPT
CPU0_LPC
GNDNS
AVDD_NS_SAS
NS_SAS1_LPT
NS_SAS1_LPC
NS_SAS0_LPT
NS_SAS0_LPC
GNDNS
VDDNS
NS_SRC1_LPT
NS_SRC1_LPC
NS_SRC0_LPT
NS_SRC0_LPC
NC
GNDSRC
AVDD_SRC
VDDSRC
SRC2_LPT
SRC2_LPC
SRC1_LPT
SRC1_LPC
vREF14_3x/TEST_SEL
CPU3_LPC
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
GNDPCI
VDDPCI
PCI4_2x
PCI3_2x
PCI2_2x
PCI1_2x
PCI0_2x
GNDPCI
VDDPCI
VDD48
48M_2x
GND48
GND96
DOT96_LPT
DOT96_LPC
AVDD96
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CKPWRGD#/PD
SRC0_LPC
VDDSRC
SRC0_LPT
TEST_MODE
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
GNDSRC
AVDD_SRC
NC
NS_SRC0_LPC
NS_SRC0_LPT
GNDCPU
VDDCPU
CPU1_LPT
CPU1_LPC
CPU0_LPT
CPU0_LPC
GNDNS
AVDD_NS_SAS
NS_SAS1_LPT
NS_SAS1_LPC
NS_SAS0_LPT
NS_SAS0_LPC
GNDNS
VDDNS
NS_SRC1_LPT
NS_SRC1_LPC
932SQL420
932SQL420
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
GNDSRC
SRC1_LPC
SRC2_LPC
SRC1_LPT
SRC2_LPT
VDDSRC
64-TSSOP
Note: Pins with ^ prefix have internal 120K pullup
Pins with v prefix have internal 120K pulldown
64-Pin MLF
Note: Pins with ^ prefix have internal 120K pullup
Pins with v prefix have internal 120K pulldown
IDT®
LOW POWER PCIE GEN2/3 & QPI CLOCK FOR INTEL-BASED SERVERS
1
932SQL420
CPU2_LPC
CPU3_LPT
CPU2_LPT
GNDXTAL
VDDXTAL
SMBDAT
VDDCPU
SMBCLK
AVDD14
GND14
GND14
VDD14
X2_25
X1_25
REV 0.8 062012
932SQL420
LOW POWER PCIE GEN2/3 & QPI CLOCK FOR INTEL-BASED SERVERS
64TSSOP Pin Descriptions
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
PIN NAME
SMBCLK
GND14
AVDD14
VDD14
vREF14_3x/TEST_SEL
GND14
GNDXTAL
X1_25
X2_25
VDDXTAL
GNDPCI
VDDPCI
PCI4_2x
PCI3_2x
PCI2_2x
PCI1_2x
PCI0_2x
GNDPCI
VDDPCI
VDD48
48M_2x
GND48
GND96
DOT96_LPT
DOT96_LPC
AVDD96
TEST_MODE
CKPWRGD#/PD
VDDSRC
SRC0_LPT
SRC0_LPC
GNDSRC
SRC1_LPC
SRC1_LPT
SRC2_LPC
SRC2_LPT
VDDSRC
AVDD_SRC
GNDSRC
NC
NS_SRC0_LPC
NS_SRC0_LPT
NS_SRC1_LPC
NS_SRC1_LPT
VDDNS
GNDNS
TYPE
IN
PWR
PWR
PWR
I/O
PWR
PWR
IN
OUT
PWR
PWR
PWR
OUT
OUT
OUT
OUT
OUT
PWR
PWR
PWR
OUT
PWR
PWR
OUT
OUT
PWR
IN
IN
PWR
OUT
OUT
PWR
OUT
OUT
OUT
OUT
PWR
PWR
PWR
N/A
OUT
OUT
OUT
OUT
PWR
PWR
DESCRIPTION
Clock pin of SMBUS circuitry, 5V tolerant
Ground pin for 14MHz output and logic.
Analog power pin for 14MHz PLL
Power pin for 14MHz output and logic
14.318 MHz reference clock. 3X drive strength as default / TEST_SEL latched input to enable
test mode. Refer to Test Clarification Table. This pin has a weak (~120Kohm) internal pull down.
Ground pin for 14MHz output and logic.
Ground pin for Crystal Oscillator.
Crystal input, Nominally 25.00MHz.
Crystal output, Nominally 25.00MHz.
3.3V power for the crystal oscillator.
Ground pin for PCI outputs and logic.
3.3V power for the PCI outputs and logic
3.3V PCI clock output
3.3V PCI clock output
3.3V PCI clock output
3.3V PCI clock output
3.3V PCI clock output
Ground pin for PCI outputs and logic.
3.3V power for the PCI outputs and logic
3.3V power for the 48MHz output and logic
3.3V 48MHz output
Ground pin for 48MHz output and logic.
Ground pin for DOT96 output and logic.
True clock of low-power push-pull differential 96MHz output. External series resistors are needed
for termination.
Complementary clock of low-power push-pull differential 96MHz output. External series resistors
are needed for termination.
3.3V power for the 48/96MHz PLL and the 96MHz output and logic
TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test
mode. Refer to Test Clarification Table.
CKPWRGD# is an active low input used to sample latched inputs and allow the device to Power
Up. PD is an asynchronous active high input pin used to put the device into a low power state.
The internal clocks and PLLs are stopped.
3.3V power for the SRC outputs and logic
True clock of low-power push-pull differential SRC output. External series resistors are needed
for termination.
Complementary clock of low-power push-pull differential SRC output. External series resistors
are needed for termination.
Ground pin for SRC outputs and logic.
Complementary clock of low-power push-pull differential SRC output. External series resistors
are needed for termination.
True clock of low-power push-pull differential SRC output. External series resistors are needed
for termination.
Complementary clock of low-power push-pull differential SRC output. External series resistors
are needed for termination.
True clock of low-power push-pull differential SRC output. External series resistors are needed
for termination.
3.3V power for the SRC outputs and logic
3.3V power for the SRC PLL analog circuits
Ground pin for SRC outputs and logic.
No Connection.
Complementary clock of low-power push-pull differential non-spreading SRC output. External
series resistors are needed for termination.
True clock of low-power push-pull differential non-spreading SRC output. External series resistors
are needed for termination.
Complementary clock of low-power push-pull differential non-spreading SRC output. External
series resistors are needed for termination.
True clock of low-power push-pull differential non-spreading SRC output. External series resistors
are needed for termination.
3.3V power for the Non-Spreading differential outputs outputs and logic
Ground pin for non-spreading differential outputs and logic.
IDT®
LOW POWER PCIE GEN2/3 & QPI CLOCK FOR INTEL-BASED SERVERS
2
932SQL420
REV 0.8 062012
932SQL420
LOW POWER PCIE GEN2/3 & QPI CLOCK FOR INTEL-BASED SERVERS
64TSSOP Pin Descriptions (cont.)
PIN #
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
PIN NAME
NS_SAS0_LPC
NS_SAS0_LPT
NS_SAS1_LPC
NS_SAS1_LPT
AVDD_NS_SAS
GNDNS
CPU0_LPC
CPU0_LPT
CPU1_LPC
CPU1_LPT
VDDCPU
GNDCPU
CPU2_LPC
CPU2_LPT
CPU3_LPC
CPU3_LPT
VDDCPU
SMBDAT
TYPE
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
I/O
DESCRIPTION
Complementary clock of low-power push-pull differential non-spreading SAS output. External
series resistors are needed for termination.
True clock of low-power push-pull differential non-spreading SAS output. External series resistors
are needed for termination.
Complementary clock of low-power push-pull differential non-spreading SAS output. External
series resistors are needed for termination.
True clock of low-power push-pull differential non-spreading SAS output. External series resistors
are needed for termination.
3.3V power for the non-spreading SAS/SRC PLL analog circuits.
Ground pin for non-spreading differential outputs and logic.
Complementary clock of low-power push-pull differential CPU output. External series resistors
are needed for termination.
True clock of low-power push-pull differential CPU output. External series resistors are needed
for termination.
Complementary clock of low-power push-pull differential CPU output. External series resistors
are needed for termination.
True clock of low-power push-pull differential CPU output. External series resistors are needed
for termination.
3.3V power for the CPU outputs and logic
Ground pin for CPU outputs and logic.
Complementary clock of low-power push-pull differential CPU output. External series resistors
are needed for termination.
True clock of low-power push-pull differential CPU output. External series resistors are needed
for termination.
Complementary clock of low-power push-pull differential CPU output. External series resistors
are needed for termination.
True clock of low-power push-pull differential CPU output. External series resistors are needed
for termination.
3.3V power for the CPU outputs and logic
Data pin of SMBUS circuitry, 5V tolerant
IDT®
LOW POWER PCIE GEN2/3 & QPI CLOCK FOR INTEL-BASED SERVERS
3
932SQL420
REV 0.8 062012
932SQL420
LOW POWER PCIE GEN2/3 & QPI CLOCK FOR INTEL-BASED SERVERS
64MLF Pin Descriptions
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
38
PIN NAME
GNDPCI
VDDPCI
PCI4_2x
PCI3_2x
PCI2_2x
PCI1_2x
PCI0_2x
GNDPCI
VDDPCI
VDD48
48M_2x
GND48
GND96
DOT96_LPT
DOT96_LPC
AVDD96
TEST_MODE
CKPWRGD#/PD
VDDSRC
SRC0_LPT
SRC0_LPC
GNDSRC
SRC1_LPC
SRC1_LPT
SRC2_LPC
SRC2_LPT
VDDSRC
AVDD_SRC
GNDSRC
NC
NS_SRC0_LPC
NS_SRC0_LPT
NS_SRC1_LPC
NS_SRC1_LPT
VDDNS
GNDNS
NS_SAS0_LPT
TYPE
PWR
PWR
OUT
OUT
OUT
OUT
OUT
PWR
PWR
PWR
OUT
PWR
PWR
OUT
OUT
PWR
IN
IN
PWR
OUT
OUT
PWR
OUT
OUT
OUT
OUT
PWR
PWR
PWR
N/A
OUT
OUT
OUT
OUT
PWR
PWR
OUT
DESCRIPTION
Ground pin for PCI outputs and logic.
3.3V power for the PCI outputs and logic
3.3V PCI clock output
3.3V PCI clock output
3.3V PCI clock output
3.3V PCI clock output
3.3V PCI clock output
Ground pin for PCI outputs and logic.
3.3V power for the PCI outputs and logic
3.3V power for the 48MHz output and logic
3.3V 48MHz output
Ground pin for 48MHz output and logic.
Ground pin for DOT96 output and logic.
True clock of low-power push-pull differential 96MHz output. External series resistors are needed
for termination.
Complementary clock of low-power push-pull differential 96MHz output. External series resistors
are needed for termination.
3.3V power for the 48/96MHz PLL and the 96MHz output and logic
TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test
mode. Refer to Test Clarification Table.
CKPWRGD# is an active low input used to sample latched inputs and allow the device to Power
Up. PD is an asynchronous active high input pin used to put the device into a low power state.
The internal clocks and PLLs are stopped.
3.3V power for the SRC outputs and logic
True clock of low-power push-pull differential SRC output. External series resistors are needed
for termination.
Complementary clock of low-power push-pull differential SRC output. External series resistors
are needed for termination.
Ground pin for SRC outputs and logic.
Complementary clock of low-power push-pull differential SRC output. External series resistors
are needed for termination.
True clock of low-power push-pull differential SRC output. External series resistors are needed
for termination.
Complementary clock of low-power push-pull differential SRC output. External series resistors
are needed for termination.
True clock of low-power push-pull differential SRC output. External series resistors are needed
for termination.
3.3V power for the SRC outputs and logic
3.3V power for the SRC PLL analog circuits
Ground pin for SRC outputs and logic.
No Connection.
Complementary clock of low-power push-pull differential non-spreading SRC output. External
series resistors are needed for termination.
True clock of low-power push-pull differential non-spreading SRC output. External series resistors
are needed for termination.
Complementary clock of low-power push-pull differential non-spreading SRC output. External
series resistors are needed for termination.
True clock of low-power push-pull differential non-spreading SRC output. External series resistors
are needed for termination.
3.3V power for the Non-Spreading differential outputs outputs and logic
Ground pin for non-spreading differential outputs and logic.
True clock of low-power push-pull differential non-spreading SAS output. External series resistors
are needed for termination.
IDT®
LOW POWER PCIE GEN2/3 & QPI CLOCK FOR INTEL-BASED SERVERS
4
932SQL420
REV 0.8 062012
932SQL420
LOW POWER PCIE GEN2/3 & QPI CLOCK FOR INTEL-BASED SERVERS
64MLF Pin Descriptions (cont.)
PIN #
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
PIN NAME
NS_SAS1_LPC
NS_SAS1_LPT
AVDD_NS_SAS
GNDNS
CPU0_LPC
CPU0_LPT
CPU1_LPC
CPU1_LPT
VDDCPU
GNDCPU
CPU2_LPC
CPU2_LPT
CPU3_LPC
CPU3_LPT
VDDCPU
SMBDAT
SMBCLK
GND14
AVDD14
VDD14
TYPE
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
I/O
IN
PWR
PWR
PWR
DESCRIPTION
Complementary clock of low-power push-pull differential non-spreading SAS output. External
series resistors are needed for termination.
True clock of low-power push-pull differential non-spreading SAS output. External series resistors
are needed for termination.
3.3V power for the non-spreading SAS/SRC PLL analog circuits.
Ground pin for non-spreading differential outputs and logic.
Complementary clock of low-power push-pull differential CPU output. External series resistors
are needed for termination.
True clock of low-power push-pull differential CPU output. External series resistors are needed
for termination.
Complementary clock of low-power push-pull differential CPU output. External series resistors
are needed for termination.
True clock of low-power push-pull differential CPU output. External series resistors are needed
for termination.
3.3V power for the CPU outputs and logic
Ground pin for CPU outputs and logic.
Complementary clock of low-power push-pull differential CPU output. External series resistors
are needed for termination.
True clock of low-power push-pull differential CPU output. External series resistors are needed
for termination.
Complementary clock of low-power push-pull differential CPU output. External series resistors
are needed for termination.
True clock of low-power push-pull differential CPU output. External series resistors are needed
for termination.
3.3V power for the CPU outputs and logic
Data pin of SMBUS circuitry, 5V tolerant
Clock pin of SMBUS circuitry, 5V tolerant
Ground pin for 14MHz output and logic.
Analog power pin for 14MHz PLL
Power pin for 14MHz output and logic
14.318 MHz reference clock. 3X drive strength as default / TEST_SEL latched input to enable
test mode. Refer to Test Clarification Table. This pin has a weak (~120Kohm) internal pull down.
Ground pin for 14MHz output and logic.
Ground pin for Crystal Oscillator.
Crystal input, Nominally 25.00MHz.
Crystal output, Nominally 25.00MHz.
3.3V power for the crystal oscillator.
vREF14_3x/TEST_SEL I/O
GND14
GNDXTAL
X1_25
X2_25
VDDXTAL
PWR
PWR
IN
OUT
PWR
IDT®
LOW POWER PCIE GEN2/3 & QPI CLOCK FOR INTEL-BASED SERVERS
5
932SQL420
REV 0.8 062012
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