RSL10
Bluetooth
)
5 Radio
System-on-Chip (SoC)
Introduction
RSL10 is an ultra−low−power, highly flexible multi−protocol
2.4 GHz radio specifically designed for use in high−performance
wearable and medical applications. With its Arm
®
Cortex
®
−M3
Processor and LPDSP32 DSP core, RSL10 supports Bluetooth low
energy technology and 2.4 GHz proprietary protocol stacks, without
sacrificing power consumption.
Key Features
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Rx Sensitivity (Bluetooth Low Energy Mode, 1 Mbps): −94 dBm
Data Rate: 62.5 to 2000 kbps
Transmitting Power: −17 to +6 dBm
Peak Rx Current = 5.6 mA (1.25 V VBAT)
Peak Rx Current = 3.0 mA (3 V VBAT)
Peak Tx Current (0 dBm) = 8.9 mA (1.25 V VBAT)
Peak Tx Current (0 dBm) = 4.6 mA (3 V VBAT)
Bluetooth 5 Certified with LE 2M PHY Support
Arm Cortex−M3 Processor Clocked at up to 48 MHz
LPDSP32 for Audio Codec
Supply Voltage Range: 1.1 − 3.3 V
Current Consumption (1.25 V VBAT):
♦
Deep Sleep, IO Wake−up: 50 nA
♦
Deep Sleep, 8 kB RAM Retention: 300 nA
♦
Audio Streaming at 7 kHz Audio BW: 1.8 mA RX, 1.8 mA TX
Current Consumption (3 V VBAT):
♦
Deep Sleep, IO Wake−up: 25 nA
♦
Deep Sleep, 8 kB RAM Retention: 100 nA
♦
Audio Streaming at 7 kHz Audio BW: 0.9 mA RX, 0.9 mA TX
384 kB of Flash Memory
Highly−integrated System−on−Chip (SoC)
Supports FOTA (Firmware Over−The−Air) Updates
WLCSP51
CASE 567MT
1 48
QFN48
CASE 485BA
RSL10
AWLYYWWG
RSL10
AWLYWW
G
(WLCSP51)
(QFN48)
XXXXXX
A
WL
Y or YY
WW
G or
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
Device
NCH−RSL10−
101WC51−ABG
NCH−RSL10−
101Q48−ABG
Package
WLCSP51
(Pb−Free)
QFN48
(Pb−Free)
Shipping
†
5000 / Tape &
Reel
3000 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2016
1
May, 2018 − Rev. 3
Publication Order Number:
RSL10/D
RSL10
FEATURES
•
Arm Cortex−M3 Processor:
A 32−bit core for
real−time applications, specifically developed to enable
high−performance low−cost platforms for a broad range
of low−power applications.
LPDSP32:
A 32−bit Dual Harvard DSP core that
efficiently supports audio codecs required for wireless
audio communication. Various codecs are available to
customers through libraries that are included in
RSL10’s development tools.
Radio Frequency Front−End:
Based on a 2.4 GHz RF
transceiver, the RFFE implements the physical layer of
the Bluetooth low energy technology standard and other
proprietary or custom protocols.
Protocol Baseband Hardware:
Bluetooth 5 certified
and includes support for a 2 Mbps RF link and custom
protocol options. The RSL10 baseband stack is
supplemented by support structures that enable
implementation of ON Semiconductor and customer
designed custom protocols.
Highly−Integrated SoC:
The dual−core architecture is
complemented by high−efficiency power management
units, oscillators, flash and RAM memories, a DMA
controller, along with a full complement of peripherals
and interfaces.
Deep Sleep Mode:
RSL10 can be put into a Deep
Sleep Mode when no operations are required. Various
Deep Sleep Mode configurations are available,
including:
♦
“IO wake−up” configuration. The power
consumption in deep sleep mode is 50 nA (1.25 V
VBAT).
♦
Embedded 32 kHz oscillator running with interrupts
from timer or external pin. The total current drain is
90 nA (1.25 V VBAT).
♦
As above with 8 kB RAM data retention. The total
current drain is 300 nA (1.25 V VBAT).
♦
With the exception of IO wake up only
configuration, the on−chip buck converter can also
be enabled to reduce current consumption in Deep
Sleep Mode (at higher VBAT voltages).
Standby Mode:
Can be used to reduce the average
power consumption for off−duty cycle operation,
ranging typically from a few ms to a few hundreds of
ms. The typical chip power consumption is 30
mA
in
Standby Mode.
Multi−Protocol Support:
Using the flexibility
provided by LPDSP32, the Arm Cortex−M3 processor,
and the RF front−end; proprietary protocols and other
custom protocols are supported.
•
Flexible Supply Voltage:
RSL10 integrates high−
efficiency power regulators and has a VBAT range of
1.1 to 3.3 V. See Table 2. RECOMMENDED
OPERATING CONDITIONS.
Highly Configurable Interfaces:
I
2
C, UART, two SPI
interfaces, PCM interface, multiple GPIOs. It also
supports a digital microphone interface (DMIC) and an
output driver (OD).
The Asynchronous Sample Rate Converter (ASRC)
Block and Audio Sink Clock Blocks
Provides a means
of synchronizing the audio sample rate between an
audio source and an audio sink. The audio sink clock
also provides a high accuracy mechanism to measure an
input clock used for the RTC or protocol timing.
Flexible Clocking Scheme:
RSL10 must be clocked
from the XTAL/PLL of the radio front−end at 48 MHz
when transmitting or receiving RF traffic. When RSL10
is not transmitting/receiving RF traffic, it can run off
the 48 MHz XTAL, the internal RC oscillators, the
32 kHz oscillator, or an external clock. A low
frequency RTC clock at 32 kHz can also be used in
Deep Sleep Mode. It can be sourced from either the
internal XTAL, the RC oscillator, or a digital input pad.
Diverse Memory Architecture:
76 kB of SRAM
program memory and 88 kB of SRAM data memory
are available. A total of 384 kB of flash is available to
store the Bluetooth stack and other applications. The
Arm Cortex−M3 processor can execute from SRAM
and/or flash.
IP Protection Feature:
Ensures that the customer’s
flash contents cannot be copied by a third party. It
prevents any core or memory from being accessed
externally after the chip has booted.
Ultra−Low Power Consumption Application
Examples:
♦
Audio Signal Streaming: IDD = 1.8 mA @ VBAT
1.25 V in Rx Mode for receiving, decoding and
sending an 7 kHz bandwidth audio signal to the SPI
interface using a proprietary custom audio protocol
from ON Semiconductor.
♦
Low Duty Cycle Advertising: IDD 1.1
mA
for
advertising at all three channels at 5 second intervals
@ VBAT 3 V, DCDC converter enabled.
RoHS Compliant Device
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RSL10
RSL10 INTERNAL BLOCK DIAGRAM
The block diagram of the RSL10 chip is shown in Figure 1.
RF
Power Management
Radio PHY
Battery
Timers
Baseband controller
DMA
IP Protection
Bluetooth 5 (LE 2M) and custom protocol
XTAL_32 kHz
Oscillators
XTAL_48 MHz
RAMs and
Flash
Bus
Arbiters
ADC
ADC (4x)
LPDSP32
32−bit Dual Harvard core
JTAG
Arm[ Cortex[-M3
Processor
SWJ−DP
Sample Rate Converter
Audio Sink Clock
Counters
I2C
Interfaces
SPI
(2x)
PCM
PWM
(2x)
DMIC
(2x)
OD UART
GPIO
Figure 1. RSL10 Block Diagram
Table 1. ABSOLUTE MAXIMUM RATINGS
Symbol
VBAT
VDDO
VSSRF
VSSA
VSSD
Vin
T functional
T storage
Parameter
Power supply voltage
I/O supply voltage
RF front−end ground
Analog ground
Digital core and I/O ground
Voltage at any input pin
Functional temperature range
Storage temperature range
Min
−
−
−0.3
−0.3
−0.3
VSSD−0.3
−40
−40
Max
3.63
3.63
−
−
−
VDDO + 0.3
85
85
Unit
V
V
V
V
V
V
°C
°C
Caution: Class 2 ESD Sensitivity, JESD22−A114−B (2000 V)
The QFN package meets 450 V CDM level
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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RSL10
Table 2. RECOMMENDED OPERATING CONDITIONS
Description
Supply voltage operating range
Symbol
VBAT
Conditions
Input supply voltage on VBAT pin (Note 1)
Min
1.18
Typ
1.25
Max
3.3
Units
V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
1. In order to be able to use a VBAT Min of 1.1 V, the following reduced operating conditions should be observed:
− Maximum Tx power 0 dBm.
− SYSCLK
≤
24 MHz.
− Functional temperature range limited to 0−50 deg C
The following trimming parameters should be used:
− VCC = 1.10 V
− VDDC = 0.92 V
− VDDM = 1.05 V, will be limited by VCC at end of battery life
− VDDRF = 1.05 V, will be limited by VCC at end of battery life. VDDPA should be disabled
RSL10 should enter in end−of−battery−life operating mode if VCC falls below 1.03 V. VCC will remain above 1.03 V if VBAT
≥
1.10 V under
the restricted operating conditions described above.
Table 3. ELECTRICAL PERFORMANCE SPECIFICATIONS
Unless otherwise noted, the specifications mentioned in the table below are valid at 25°C at VBAT = VDDO = 1.25 V.
Description
OVERALL
Current consumption RX,
V
BAT
= 1.25 V, low latency
Current consumption TX,
V
BAT
= 1.25 V, low latency
I
VBAT
RX Mode, ON Semiconductor
proprietary audio streaming protocol at
7 kHz audio BW, 5.5 ms delay.
TX Mode, ON Semiconductor
|proprietary audio streaming protocol at
7 kHz audio BW, 5.5 ms delay. Transmit
power: 0 dBm
RX Mode, ON Semiconductor
proprietary audio streaming protocol at
7 kHz audio BW, 37 ms delay.
Wake up from wake up pin.
Embedded 32 kHz oscillator running
with interrupts from timer or external pin.
As Ids2 but with 8 kB RAM data
retention.
Digital blocks and memories are not
clocked and are powered at a reduced
voltage.
RX Mode, ON Semiconductor
proprietary audio streaming protocol at
7 kHz audio BW, 5.5 ms delay.
TX Mode, ON Semiconductor
proprietary audio streaming protocol at
7 kHz audio BW, 5.5 ms delay. Transmit
power: 0 dBm
Wake up form wake up pin.
Embedded 32 kHz oscillator running
with interrupts from timer or external pin.
As Ids2 but with 8 kB RAM data
retention.
Digital blocks and memories are not
clocked and are powered at a reduced
voltage.
−
1.8
−
mA
Symbol
Conditions
Min
Typ
Max
Units
I
VBAT
−
1.8
−
mA
Current consumption RX,
V
BAT
= 1.25 V
Deep sleep current,
example 1, V
BAT
= 1.25 V
Deep sleep current,
example 2, V
BAT
= 1.25 V
Deep sleep current,
example 3, V
BAT
= 1.25 V
Standby Mode current,
V
BAT
= 1.25 V
Current consumption RX,
V
BAT
= 3 V
Current consumption TX,
V
BAT
= 3 V
I
VBAT
−
1.15
−
mA
Ids1
Ids2
Ids3
Istb
−
−
−
−
50
90
300
30
−
−
−
−
nA
nA
nA
mA
I
VBAT
−
0.9
−
mA
I
VBAT
−
0.9
−
mA
Deep sleep current,
example 1, V
BAT
= 3 V
Deep sleep current,
example 2, V
BAT
= 3 V
Deep sleep current,
example 3, V
BAT
= 3 V
Standby Mode current,
V
BAT
= 3 V
Ids1
Ids2
Ids3
Istb
−
−
−
−
25
40
100
17
−
−
−
−
nA
nA
nA
mA
EEMBC ULPMark BENCHMARK, CORE PROFILE
ULPMark CP 3.0 V
Arm Cortex−M3 processor running from
RAM, VBAT= 3.0 V, IAR C/C++
Compiler for ARM 8.20.1.14183
−
1090
−
ULP
Mark
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RSL10
Table 3. ELECTRICAL PERFORMANCE SPECIFICATIONS
(continued)
Unless otherwise noted, the specifications mentioned in the table below are valid at 25°C at VBAT = VDDO = 1.25 V.
Description
Symbol
Conditions
Min
Typ
Max
Units
EEMBC ULPMark BENCHMARK, CORE PROFILE
ULPMark CP 2.1 V
Arm Cortex−M3 processor running from
RAM, VBAT= 2.1 V, IAR C/C++
Compiler for ARM 8.20.1.14183
−
1260
−
ULP
Mark
EEMBC CoreMark BENCHMARK for the Arm Cortex−M3 Processor and the LPDSP32 DSP
Arm Cortex−M3 processor
running from RAM
LPDSP32 running from RAM
At 48 MHz SYSCLK. Using the IAR
8.10.1 C compiler, certified
At 48 MHz SYSCLK
Using the 2017.03−SP3−2 release of
the Synopsys LPDSP32 C compiler
At 48 MHz SYSCLK
−
−
159
133
−
−
Core
Mark
Core
Mark
Core
Mark/
mA
Core
Mark/
mA
Arm Cortex−M3 processor and
LPDSP32 running from RAM,
VBAT = 1.25 V
Arm Cortex−M3 processor and
LPDSP32 running from RAM,
VBAT = 3 V
−
108
−
At 48 MHz SYSCLK
−
257
−
INTERNALLY GENERATED VDDC: Digital Block Supply Voltage
Supply voltage: operating range
Supply voltage: trimming range
Supply voltage: trimming step
VDDC
VDDC
RANGE
VDDC
STEP
VDDM
VDDM
RANGE
VDDM
STEP
VDDRF
VDDRF
RANGE
VDDRF
STEP
VDDPA
VDDPA
RANGE
VDDPA
STEP
DCDC
STEP
0.92
0.75
−
1.15
−
10
1.32
(Note 2)
1.38
−
V
V
mV
INTERNALLY GENERATED VDDM: Memories Supply Voltage
Supply voltage: operating range
Supply voltage: trimming range
Supply voltage: trimming step
1.05
0.75
−
1.15
−
10
1.32
(Note 3)
1.38
−
V
V
mV
INTERNALLY GENERATED VDDRF: Radio Front end supply voltage
Supply voltage: operating range
Supply voltage: trimming range
Supply voltage: trimming step
1.00
0.75
−
1.10
−
10
1.32 (Notes
4 and 5)
1.38
−
V
V
mV
INTERNALLY GENERATED VDDPA: Optional Radio Power Amplifier Supply Voltage
Supply voltage: operating range
Supply voltage: trimming range
Supply voltage: trimming step
Supply voltage: trimming step
1.05
1.05
−
−
1.3
−
10
10
1.68
1.68
−
−
V
V
mV
mV
VDDO PAD SUPPLY VOLTAGE: Digital Level High Voltage
Digital I/O supply
VDDO
1.1
1.25
3.3
V
INDUCTIVE BUCK DC−DC CONVERTER
VBAT range when the DC−DC
converter is active (Note 6)
VBAT range when the LDO is
active
Output voltage: trimming range
Supply voltage: trimming step
POWER−ON RESET
POR voltage
VBAT
POR
0.4
0.8
1.0
V
DCDC
IN_RANGE
1.4
1.1
1.1
−
−
−
1.2
10
3.3
3.3
1.32
−
V
V
V
mV
LDO
IN_RANGE
DCDC
OUT_RANGE
DCDC
STEP
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