NCV891234, NCV891334
2 MHz Low-I
Q
Dual-Mode
Step-Down Regulator for
Automotive
The NCV891x34 is a Dual Mode regulator intended for Automotive,
battery−connected applications that must operate with up to a 45 V
input supply. Hybrid Low Power Mode allows the NCV891x34 to
operate either as a PWM Buck Converter or as a Low Drop−Out Linear
Regulator, and the NCV891x34 is suitable for systems with Low Noise
and Low Quiescent Current requirements often encountered in
automotive driver information systems. A reset (with fixed delay) and
a fault pin (flagging low input voltage and high temperature warnings)
simplify interfacing with a microcontroller.
Two pins are provided to synchronize switching to a clock, or to
another NCV891x34. The NCV891x34 also provides several protection
features expected in automotive power supply systems such as current
limit, short circuit protection, and thermal shutdown. In addition, the
high switching frequency produces low output voltage ripple even
when using small inductor values and an all−ceramic output filter
capacitor – forming a space−efficient switching regulator solution.
Features
www.onsemi.com
1
DFN12
MW SUFFIX
CASE 506CE
MARKING DIAGRAM
891x34
XX
ALYWG
G
891x34XX = Specific Device Code
x
= 2, 3
XX
= 33, 50
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Device
(Note: Microdot may be in either location)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
40
mA
Iq in Light Load Condition
2.0 A Maximum Output Current in PWM Mode in NCV891234
3.0 A Maximum Output Current in PWM Mode in NCV891334
Internal N−channel Power Switch
V
IN
Operating Range 3.7 V to 36 V, Withstands Load Dump to 45 V
Logic Level Enable Pin can be Tied to Battery
Fixed Output Voltage of 5.0 V or 3.3 V with
±2%
Accuracy
2 MHz Free−running Switching Frequency
Input and Output Synchronization Pins
NCV Prefix for Automotive Requiring Site and Control Changes
Wettable Flanks DFN (pin edge plating)
These Devices are Pb−Free and are RoHS Compliant
Safety−Vision Systems
Audio, Infotainment
Instrumentation
Telematics
VIN
VIN
CIN
VIN2
DRV
SYNCO
SYNCO
RESET
RSTB
GND
SYNCI
FLTB
EN
ENABLE
SYNCI
FAULT
BST
VOUT
PIN CONNECTIONS
VIN
VIN2
DRV
SYNCO
RSTB
1
SW
BST
VOUT
EN
SYNCI
FLTB
(Top View)
Typical Applications
CDRV
DBST
NCV891x34
SW
CBST
DFW
COUT
L1
VOUT
GND
ORDERING INFORMATION
See detailed ordering and shipping information on page 10 of
this data sheet.
Figure 1. Application Schematic
©
Semiconductor Components Industries, LLC, 2016
1
June, 2016 − Rev. 0
Publication Order Number:
NCV891334/D
NCV891234, NCV891334
CDRV
VIN
VIN
SW
DBST
L1
VOUT
CIN
VIN 2
3.3 V
Reg
DRV
Oscillator
Low
ON
Enable
Sync
Out
Sync
In
+
+
CBST
PWM
LOGIC
OFF
DFW
COUT
BST
VOUT
S
2A, 3A
detector
+
−
+
+
−
SYNCO
SYNCO
comp
EN
EN
TSD
Soft−Start
RESET
VOLTAGES
MONITORS
SYNCI
SYNCI
RESET
RSTB
Switcher Supply
ON
LINEAR
REGULATOR
ON
OVLD
+
−
+
Logic
MODE
SELECTION
GND
FLTB
NCV891234, NCV891334
Fault
Detection
FAULT
Figure 2. Simplified Block Diagrams
www.onsemi.com
2
NCV891234, NCV891334
Table 1. PIN FUNCTION DESCRIPTION
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
EPAD
Pin Name
VIN
VIN2
DRV
SYNCO
RSTB
GND
FLTB
SYNCI
EN
VOUT
BST
SW
Description
Input voltage from battery. Place an input filter capacitor in close proximity to this pin.
Input voltage pin – must be connected to VIN (pin 1)
Output voltage to provide a regulated voltage to the Power Switch gate driver.
Out−of−phase synchronization output. Turn−on of the Power Switch causes the SYNCO signal to fall
(and rise half a switching period later).
Reset function. Open drain output, pulling down to ground when the output voltage is out of regulation.
Battery return, and output voltage ground reference.
Fault flag indicating various fault conditions for the part
Synchronization input. Connecting an external clock to this pin synchronizes switching to the rising edge of
the SYNCI signal.
This TTL compatible Enable input allows the direct connection of Battery as the enable signal. Grounding this
input stops switching and reduces quiescent current draw to a minimum.
Output voltage feedback and LDO output. Feedback of output voltage used for regulation, as well as LDO
output in LDO mode.
Bootstrap input provides drive voltage higher than VIN to the N−channel Power Switch for minimum
switch Rdson and highest efficiency.
Switching node of the Regulator. Connect the output inductor and cathode of the freewheeling diode to
this pin.
Connect to Pin 6 (electrical ground) and to a low thermal resistance path to the ambient temperature
environment.
Table 2. ABSOLUTE MAXIMUM RATINGS
Rating
Min/Max Voltage VIN
Max Voltage VIN to SW
Min/Max Voltage SW
Min Voltage SW − 20 ns
Min/Max Voltage EN
Min/Max Voltage BST
Min/Max Voltage BST to SW
Min/Max Voltage SYNCI, RSTB and FLTB
Min/Max Voltage VOUT
Min/Max Voltage DRV, SYNCO
Thermal Resistance, DFN12−4x4 Junction–to–Ambient (Note 1)
Storage Temperature Range
Operating Junction Temperature Range
ESD Withstand Voltage (Note 2) − Human Body Model
Moisture Sensitivity
Peak Reflow Soldering Temperature (Note 3)
T
J
VESD
MSL
R
θJA
Symbol
Value
−0.3 to 45
45
−0.7 to 40
−3.0
−0.3 to 40
−0.3 to 43
−0.3 to 3.6
−0.3 to 6
−0.3 to 18
−0.3 to 3.6
35
−55 to +150
−40 to +150
2.0
Level 1
260
°C
Unit
V
V
V
V
V
V
V
V
V
V
°C/W
°C
°C
kV
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Value based on 4 layers of 645 mm
2
(or 1 in
2
) of 1 oz copper thickness on FR4 PCB substrate.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
Latchup Current Maximum Rating:
v150
mA per JEDEC standard: JESD78
3. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D
www.onsemi.com
3
NCV891234, NCV891334
Table 3. ELECTRICAL CHARACTERISTICS
V
IN
= 4.5 to 28 V, V
EN
= 5 V, V
BST
= V
SW
+ 3 V, C
DRV
= 0.1
mF,
for typical values T
J
= 25°C, min/max values are valid for T
J
= −40°C to
150°C unless noted otherwise, and are guaranteed by test, design or statistical correlation (Notes 4, 5)
Parameter
QUIESCENT CURRENT
Quiescent Current, enabled
Quiescent Current, shutdown
UNDERVOLTAGE LOCKOUT – VIN (UVLO)
UVLO Start Threshold
UVLO Stop Threshold
UVLO Hysteresis
SOFT−START (SS)
Soft−Start Completion Time
OUTPUT VOLTAGE
Output Voltage during regulation
100
mA
< I
OUT
< 2.5 A
5.0 V option
3.3 V option
V
OUTreg
4.9
3.234
5.0
3.3
5.1
3.366
V
t
SS
0.8
1.4
2.0
ms
V
IN
rising
V
IN
falling
V
UVLSTT
V
UVLSTP
V
UVLOHY
4.1
3.1
0.4
4.5
3.7
1.4
V
V
V
V
IN
= 13.2 V, I
OUT
= 100
mA,
25°C
V
IN
= 13.2 V, V
EN
= 0 V, 25°C
I
q
I
qSD
40
9
49
12
mA
mA
Test Conditions
Symbol
Min
Typ
Max
Unit
OSCILLATOR
Frequency
VIN FREQUENCY FOLDBACK MONITOR
Frequency Foldback Threshold
V
IN
rising
V
IN
falling
Frequency Foldback Hysteresis
MODE TRANSITION
Normal to Low−Iq mode Current Threshold
Mode Transition Duration
Switcher to Linear
Linear to Switcher
Minimum time in Normal Mode before
starting to monitor output current
Linear to switcher transition
at high Vin
at low Vin
PEAK CURRENT LIMIT
Current Limit Threshold NCV891334
Current Limit Threshold NCV891234
POWER SWITCH
ON Resistance
Leakage current VIN to SW
Minimum ON Time
Minimum OFF Time
V
BST
= V
SW
+ 3.0 V
V
SW
= 0, −40°C
v
T
J
v
85°C
Measured at SW pin
Measured at SW pin
At F
SW
= 2 MHz (normal)
At F
SW
= 500 kHz (max duty ratio)
R
DSON
I
LKSW
t
ONMIN
t
OFFMIN
30
30
50
70
45
180
360
10
70
mW
mA
ns
ns
I
LIM
I
LIM
3.9
2.9
4.4
3.25
4.9
3.6
A
A
I
NtoL
t
SWtoLIN
t
LINtoSW
t
SWblank
3
300
1
500
40
mA
ms
2
ms
V
V
OUT
= 3.3 V
V
LINtoSW(HV)
V
LINtoSW(LV)
19
3.6
28
4.5
V
V
FLDUP
V
FLDDN
V
FLDHY
18.4
18
0.2
0.3
20
19.8
0.4
V
4.5 < V
IN
< 18 V
20 V < V
IN
< 28 V
F
SW
F
SW(HV)
1.8
0.9
2.0
1.0
2.2
1.1
MHz
4. Refer to ABSOLUTE MAXIMUM RATINGS and APPLICATION INFORMATION for Safe Operating Area.
5. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at T
J
= T
A
= 25°C. Low
duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
www.onsemi.com
4
NCV891234, NCV891334
Table 3. ELECTRICAL CHARACTERISTICS
V
IN
= 4.5 to 28 V, V
EN
= 5 V, V
BST
= V
SW
+ 3 V, C
DRV
= 0.1
mF,
for typical values T
J
= 25°C, min/max values are valid for T
J
= −40°C to
150°C unless noted otherwise, and are guaranteed by test, design or statistical correlation (Notes 4, 5)
Parameter
SLOPE COMPENSATION
Ramp Slope
(With respect to switch current)
LOW POWER LINEAR REGULATOR
Line Regulation
Load Regulation
Power Supply Rejection
Current Limit
Output clamp current
SHORT CIRCUIT DETECTOR
Switching frequency in short−circuit condi-
tion
Analog Foldback
Analog foldback – high V
IN
Hiccup Mode
RESET
Leakage current into RSTB pin
Output voltage threshold at which the RSTB
signal goes low
V
OUT
decreasing
5.0 V option
3.3 V option
V
OUT
increasing
5.0 V option
3.3 V option
From V
OUT
< V
RESET
to
RSTB pin going low
From V
OUT
> V
RESET
+ V
REShys
to
high RSTB
R
RSTBpullup
= V
OUTreg
/1 mA, V
OUT
> 1 V
V
RESET
4.50
2.97
V
REShys
25
17
t
filter
t
delay
V
RSTBlow
10
14
16
60
40
100
66
25
18
0.4
ms
ms
V
4.625
3.05
4.75
3.14
mV
1
mA
V
kHz
V
OUT
= 0 V, 4.5 V < V
IN
< 18 V
V
OUT
= 0 V, 20 V < V
IN
< 28 V
F
SWAF
F
SWAFHV
F
SWHIC
450
225
24
550
275
32
650
325
40
V
OUT
= V
OUTreg(typ)
+ 10%
I
OUT
= 5 mA, 6 V < V
IN
< 18 V
V
IN
= 13.2 V, 0.1 mA < I
OUT
< 50 mA
V
OUT(ripple)
= 0.5 Vp−p, F = 100 Hz
V
REG(line)
V
REG(load)
PSRR
I
LIN(lim)
I
CL(OUT)
50
0.5
1.0
5
5
65
80
1.5
25
35
mV
mV
dB
mA
mA
4.5 < V
IN
< 18 V
20 V < V
IN
< 28V
S
ramp
S
ramp(HV)
1.45
0.65
2.0
1.0
2.8
1.3
A/ms
Test Conditions
Symbol
Min
Typ
Max
Unit
Hysteresis on RSTB threshold
Noise−filtering delay
Restart Delay time
Low RSTB voltage
GATE VOLTAGE SUPPLY (DRV pin)
Output Voltage
DRV UVLO START Threshold
DRV UVLO STOP Threshold
DRV UVLO Hysteresis
DRV Current Limit
VIN OVERVOLTAGE SHUTDOWN MONITOR
Overvoltage Stop Threshold
Overvoltage Start Threshold
Overvoltage Hysteresis
ENABLE (EN)
Logic low threshold voltage
Logic high threshold voltage
EN pin input current
V
DRV
V
DRVSTT
V
DRVSTP
V
DRVHYS
V
DRV
= 0 V
I
DRVLIM
3.1
2.7
2.5
50
21
3.3
2.9
2.8
3.5
3.05
3.0
200
50
V
V
V
mV
mA
V
IN
increasing
V
IN
decreasing
V
OVSTP
V
OVSTT
V
OVHY
36.5
36.0
0.25
37.7
37.3
0.40
39.0
38.8
0.50
V
V
V
V
ENlow
V
ENhigh
I
ENbias
0.8
2
0.2
1
V
V
mA
4. Refer to ABSOLUTE MAXIMUM RATINGS and APPLICATION INFORMATION for Safe Operating Area.
5. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at T
J
= T
A
= 25°C. Low
duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
www.onsemi.com
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
