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74VHC240 Octal Buffer/Line Driver with 3-STATE Outputs
April 2007
74VHC240
Octal Buffer/Line Driver with 3-STATE Outputs
Features
■
High Speed: t
PD
=
3.6ns (typ) at T
A
=
25°C
■
Low power dissipation: I
CC
=
4µA (max) @ T
A
=
25°C
■
High noise immunity: V
NIH
=
V
NIL
=
28% V
CC
(min.)
■
Power down protection is provided on all inputs
■
Low noise: V
OLP
=
0.9V (max.)
■
Pin and function compatible with 74HC240
tm
General Description
The VHC240 is an advanced high speed CMOS octal
bus buffer fabricated with silicon gate CMOS technology.
It achieves high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low
power dissipation. The VHC240 is an inverting 3-STATE
buffer having two active-LOW output enables. This
device is designed to drive buslines or buffer memory
address registers.
An input protection circuit ensures that 0V to 7V can be
applied to the input pins without regard to the supply
voltage. This device can be used to interface 5V to 3V
systems and two supply systems such as battery
backup. This circuit prevents device destruction due to
mismatched supply and input voltages.
Ordering Information
Order Number
74VHC240M
74VHC240SJ
74VHC240MTC
Package
Number
M20B
M20D
MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the
ordering number. Pb-Free package per JEDEC J-STD-020B.
> Loading file E:\车机项目\A5V5_MA\A5V5_v1\Debug\a5v5.s19 in PROGRAM MEMORY area...
FILE : line 195: Address 0x1019 is out of range and is ignored!
FILE : line 195: Addres ......
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该机还搭载了...[详细]
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受惠平板电脑、智慧型手机与行动装置等消费性电子商品亮丽表现，半导体设备的采购需求仍将持续。SEMI在报告中指出，2011年半...[详细]
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