FAN54040 - FAN54047— USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support
FAN54040 — FAN54047
USB-OTG, 1.55 A, Li-Ion Switching Charger with Power
Path and 2.3 A Production Test Support
Features
Fully Integrated, High-Efficiency Charger for Single-Cell
Li-Ion and Li-Polymer Battery Packs
Pow er Path Circuit Ensures Fast System Startup w ith a
Dead Battery w hen VBUS is Connected
1.55 A Maximum Charge Current
Float Voltage Accuracy:
-
-
±0.5%
at 25°C
±1%
from 0 to 125°C
Description
The FAN5404X family includes I C controlled 1.55 A USB-
compliant sw itch-mode chargers w ith pow er path operation
and USB OTG boost operation. Integrated w ith the charger,
the IC supports production test mode, w hich provides 4.2 V
at up to 2.3 A to the system.
To facilitate fast system startup, the IC includes a pow er
path circuit, w hich disconnects the battery from the system
rail, ensuring that the system can pow er up quickly follow ing
a VBUS connection. The pow er path circuit ensures that the
system rail stays up w hen the charger is plugged in, even if
the battery is dead or shorted.
The charging parameters and operating modes are
2
programmable through an I C Interface that operates up to
3.4 Mbps. The charger and boost regulator circuits sw itch at
3 MHz to minimize the size of external passive components.
The FAN5404X provides battery charging in three phases:
conditioning, constant current, and constant voltage. The
integrated circuit automatically restarts the charge cycle
w hen the battery falls below a voltage threshold. If the input
source is removed, the IC enters a high-impedance mode
blocking battery current from leaking to the input. Charge
2
status is reported back to the host through the I C port.
Dynamic input voltage control prevents a w eak adapter’s
voltage from collapsing, ensuring charging capability from
such adapters.
The FAN5404X is available in a 25-bump, 0.4 mm pitch,
WLCSP package.
VBUS
C
BUS
PGND
PMID
C
MID
GATE
Q5
2
±5%
Input and Charge Current Regulation Accuracy
Temperature-Sense Input Prevents Auto-Charging for
JEITA Compliance
Thermal Regulation and Shutdow n
4.2 V at 2.3 A Production Test Mode
5 V, 500 mA Boost Mode for USB OTG
28 V Absolute Maximum Input Voltage
6 V Maximum Input Operating Voltage
2
Programmable through High-Speed I C Interface
(3.4 Mb/s) w ith Fast Mode Plus Compatibility
-
-
-
-
Input Current
Fast-Charge / Termination Current
Float Voltage
Termination Enable
3 MHz Synchronous Buck PWM Controller w ith
Wide Duty Cycle Range
Small Footprint 1
µH
External Inductor
Safety Timer w ith Reset Control
Dynamic Input Voltage Control
Very Low Battery Current w hen Charger Inactive
SW
SYS
L1
C
SYS
SYSTEM
LOAD
Applications
Cell Phones, Smart Phones, PDAs
Tablet, Portable Media Players
Gaming Device, Digital Cameras
POK_B
ILIM
SDA
SCL
DIS
STAT
AGND
FAN5404X
External
PMOS
VBAT
C
BAT
NTC
REF
R
REF
BATTERY
C
REF
T
+
All trademarks are the property of their respective owners.
Figure 1. Typical Application
© 2012 Semiconductor Components Industries, LLC.
December-2017, Rev. 2
Publication Order Number:
FAN54041/D
FAN54040 - FAN54047— USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support
Ordering Information
Part Number
FAN54040UCX
FAN54041UCX
FAN54042UCX
FAN54045UCX
FAN54046UCX
(1)
(1)
(1)
Temperature Range
Package
PN Bits:
IC_INFO[5:3]
000
001
Packing Method
-40 to 85°C
25-Bump, Wafer-Level
Chip-Scale Package
(WLCSP), 0.4 mm Pitch
010
101
110
110
Tape and Reel
FAN54047UCX
Note:
1. Contact ON Semiconductor Sales for availability.
Table 1. Feature Comparison Summary
Part Number
FAN54040
FAN54041
FAN54042
FAN54045
FAN54046
FAN54047
Slave Address
1101011
1101011
1101011
1101011
1101011
1101011
Automatic Charge
Yes
No
Yes
No
No
Yes
Battery Absent Behavior
Off
Off
On
Off
On
On
E1 Pin
POK_B
POK_B
POK_B
ILIM
ILIM
ILIM
www.onsemi.com
2
FAN54040 - FAN54047— USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support
Block Diagram
VBUS
C
BUS
PGND
Q3
Q1
Q1A
Q1B
PMID
C
MID
CHARGE
PUMP
IBUS &
VBUS
CONTROL
SW
PWM
MODULATOR
Q2
L1
AGND
C
SYS
SYS
VBUS OVP
POWER OK
PGND
SYSTEM
LOAD
Q5
GATE
CC and CV
Battery
Charger
I2C INTERFACE
LOGIC AND CONTROL
TEMP
SENSE
Q4
Q4A
Q4B
External
PMOS
POK_B
ILIM
SDA
SCL
DIS
STAT
VBAT
C
BAT
NTC
REF
R
REF
BATTERY
C
REF
T
+
PMID
Greater than V
BAT
Less than V
BAT
Q1A
ON
OFF
Q1B
OFF
ON
SYS
Greater than V
BAT
Less than V
BAT
Q4A
ON
OFF
Q4B
OFF
ON
Figure 2. IC and System Block Diagram
Table 2. Recommended External Components
Component
L1
C
BAT,
C
SYS
C
MID
C
BUS,
Q5
C
REF
Description
1
µH,
20%, 2.2 A, 2016
10
µF,
20%, 6.3 V, X5R, 0603
4.7
µF,
10%, 6.3 V, X5R, 0603
1.0
µF,
10%, 25 V, X5R, 0603
PMOS,12 V, 16 mΩ, MLP2x2
1
µF,
10%, 6.3 V, X5R, 0402
Vendor
Taiyo Yuden
MAKK2016T1R0M
or Equivalent
Murata: GRM188R60J106M
TDK: C1608X5R0J106M
Murata: GRM188R60J475K
TDK: C1608X5R0J475K
Murata GRM188R61E105K
TDK:C1608X5R1E105M
ON Semiconductor FDMA905P
Parameter
L
DCR (Series R)
C
C
(2)
Typ.
1.0
75
10
4.7
1.0
16
1.0
Unit
µH
mΩ
µF
µF
µF
mΩ
µF
C
R
DS(ON)
C
Note:
2. 6.3 V rating is sufficient for C
MID
since PMID is protected from over-voltage surges on VBUS by Q3.
www.onsemi.com
3
FAN54040 - FAN54047— USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support
Pin Configuration
SDA
A1
PGND
A2
SW
A3
PMID VBUS
A4
A5
A5
A4
A3
A2
A1
SCL
B1
B2
B3
B4
B5
B5
B4
B3
B2
B1
DIS
C1
C2
C3
C4
GATE
C5
C5
C4
C3
C2
C1
STAT
D1
D2
SYS
D3
VBAT
D4
NTC
D5
D5
D4
D3
D2
D1
POK_B AGND
E1
E2
E3
E4
REF
E5
E5
E4
E3
E2
E1
Figure 3. Top View
Figure 4. Bottom View
Pin Definitions
Pin #
A1
B1
C1
D1
Name
SDA
SCL
DIS
STAT
Description
I C Interface Serial Data.
This pin should not be left floating.
I C Interface Serial Clock.
This pin should not be left floating.
Disable.
If this pin is held HIGH, Q1 and Q3 are turned off, creating a HIGH Z condition at VBUS and
the PWM converter is disabled.
Status.
Open-drain output indicating charge status. The IC pulls this pin LOW w hen charge is in
progress; can be used to signal the host processor w hen a fault condition occurs.
Pow er OK (FAN54040-2).
Open-drain output that pulls LOW w hen VBUS is plugged in and the battery
has risen above V
LOWV
. This signal is used to signal the host processor that it can begin to draw
significant current.
Input Current Lim it (FAN54045-7).
Controls input current limit in Auto-Charge Mode. When LOW, input
current is limited to 100 mA maximum. When HIGH, input current is limited to 500 mA. In 32-Second
Mode, the input current limit is set by the I
BUSLIM
bits.
Pow er Ground.
Pow er return for gate drive and pow er transistors. The connection from this pin to the
bottom of C
MID
should be as short as possible.
Analog Ground.
All IC signals are referenced to this node.
Sw itching Node.
Connect to output inductor.
System Supply.
Output voltage of the sw itching charger and input to the pow er path controller. Bypass
SYS to PGND w ith a 10 μF capacitor.
Pow er Input Voltage.
Pow er input to the charger regulator, bypass point for the input current sense.
Bypass w ith a minimum of a 4.7
µF,
6.3 V capacitor to PGND.
Battery Voltage.
Connect to the positive (+) terminal of the battery pack. Bypass w ith a 10
µF
capacitor
to PGND. VBAT is a pow er path connection.
Charger Input Voltage
and USB-OTG output voltage. Bypass w ith a 1
µF
capacitor to PGND.
External MOSFET Gate.
This pin controls the gate of an external P-channel MOSFET transistor used to
augment the internal ideal diode. The source of the P-channel MOSFET should be connected to SYS
and the drain should be connected to VBAT.
Therm istor input.
The IC compares this node w ith taps on a resistor divider from REF to inhibit auto-
charging w hen the battery temperature is outside of permitted fast-charge limits.
Reference Voltage.
REF is a 1.8 V regulated output.
2
2
E1
POK_B
E1
ILIM
A2 – D2
E2
A3 – C3
D3 – E3
A4 – C4
D4 – E4
A5 – B5
C5
PGND
AGND
SW
SYS
PMID
VBAT
VBUS
GATE
D5
E5
NTC
REF
www.onsemi.com
4
FAN54040 - FAN54047— USB-OTG,1.55 A Li-Ion Switching Charger with Power Path and 2.3 A Production Test Support
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable
above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition,
extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute
maximum ratings are stress ratings only.
Symbol
V
BUS
V
I
V
O
dV
BUS
dt
Parameter
Voltage on VBUS Pin
Voltage on PMID Voltage Pin
Voltage on SW, SYS, VBAT, STAT, DIS Pins
Voltage on Other Pins
Maximum V
BUS
Slope Above 5.5 V w hen Boost or Charger Active
Electrostatic Discharge
Protection Level
Human Body Model per JESD22-A114
Charged Device Model per JESD22-C101
(4)
Min.
-0.3
-1.0
–0.3
–0.3
–0.3
Max.
28.0
7.0
7.0
6.5
(3)
Unit
V
V
V
V/µs
V
kV
Continuous
Pulsed, 100 ms Maximum Non-Repetitive
4
2000
500
15
8
–40
–65
+150
+150
+260
ESD
IEC 61000-4-2 System ESD
T
J
T
STG
T
L
Junction Temperature
Storage Temperature
USB Connector
Pins (V
BUS
to GND)
Air Gap
Contact
°C
°C
°C
Lead Soldering Temperature, 10 Seconds
Note:
3. Lesser of 6.5 V or V
I
+ 0.3 V.
4. Guaranteed if C
BUS
≥1 µF and C
MID
≥ 4. 7µF.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating
conditions are specified to ensure optimal performance to the datasheet specifications. ON Semiconductor does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
BUS
V
BAT(MAX)
−
dV
BUS
dt
Parameter
Supply Voltage
Maximum Battery Voltage w hen Boost enabled
Negative VBUS Slew Rate during VBUS Short Circuit,
C
MID
< 4.7 µF,
see VBUS Short While Charging
Ambient Temperature
Junction Temperature
(see Thermal Regulation and Protection section)
T
A
< 60°C
T
A
> 60°C
Min.
4
Max.
6
4.5
4
2
Unit
V
V
V/µs
°C
°C
T
A
T
J
–30
–30
+85
+120
Thermal Properties
Junction-to-ambient thermal resistance is a function of application and board layout. This data is measured w ith four-layer
2s2p boards in accordance to JEDEC standard JESD51. Special attention must be paid not to exceed junction temperature
T
J(max)
at a given ambient temperature T
A
.
For measured data, see Table 18.
Symbol
θ
JA
θ
JB
Junction-to-PCB Thermal Resistance
Parameter
Junction-to-Ambient Thermal Resistance
(see also Figure 18)
Typical
50
20
Unit
°C/W
°C/W
www.onsemi.com
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
