Si5381/82 Rev. E Reference Manual
Overview
This Reference Manual is intended to provide system, PCB design, signal integrity, and
software engineers the necessary technical information to successfully use the
Si5381/82 devices in end applications. The official device specifications can be found in
the Si5381/82 datasheet.
The Si5381/82 is a high performance jitter attenuating clock multiplier which integrates
four/two any-frequency DSPLLs for applications that require maximum integration and in-
dependent timing paths. A single low phase noise XO connected to the XA/XB input pins
provides the reference for the device. The device supports ultra-low phase noise 4G/LTE
clock generation and low jitter general-purpose clock synthesis from a single device.
Each DSPLL has access to any of the four inputs and can provide low jitter clocks on
any of the device outputs. Based on fourth generation DSPLL technology, these devices
provide any-frequency conversion with typical jitter performance under 100 fs (4G/LTE
frequency outputs). Each DSPLL supports independent free-run, holdover modes of op-
eration, as well as automatic and hitless input clock switching. The Si5381/82 is pro-
grammable via an SPI or I
2
C serial interface with in-circuit programmable non-volatile
memory so that it always powers up in a known configuration.
RELATED DOCUMENTS
• Si5381/82 Data Sheet
• Si5381/82 Device Errata
• Si5381/82A-E-EVB User Guide
• Si5381/82A-E-EVB Schematics, BOM &
Layout
• IBIS models
• To download evaluation board design and
support files, go to:
http://www.silabs.com/Si538x-4x-EVB
• JESD204B subclass 0 and subclass 1
support
Work Flow Expectations with ClockBuilder
™
Pro and the Register Map
This reference manual is to be used to describe all the functions and features of the parts in the product family with register map details
on how to implement them. It is important to understand that the intent is for customers to use the ClockBuilder
™
Pro software to pro-
vide the initial configuration for the device. Although the register map is documented, all the details of the algorithms to implement a
valid frequency plan are fairly complex and are beyond the scope of this document. Real-time changes to the frequency plan and other
operating settings are supported by the devices. However, describing all the possible changes is not a primary purpose of this docu-
ment. Refer to Applications Notes and Knowledge Base article links within the ClockBuilder Pro GUI for information on how to imple-
ment the most common, real-time frequency plan changes.
silabs.com
| Building a more connected world.
Rev. 0.9
Table of Contents
1. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 DSPLL .
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. 5
. 7
. 8
. 9
.10
.10
.12
1.2 Si5381/82 LTE Frequency Configuration .
1.4 DSPLL Loop Bandwidth . . .
1.4.1 Fastlock . . . . . . .
1.4.2 Holdover Exit Bandwidth .
1.5 Dividers Overview
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1.3 Si5381/82 Configuration for JESD204B subclass 1 Clock Generation .
2. Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1 Reset and Initialization . . . . . . . . . . .
2.1.1 Updating Registers During Device Operation .
2.1.2 NVM Programming . . . . . . . . . .
2.2 Free Run Mode .
2.4 Locked Mode .
2.5 Holdover Mode
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2.3 Lock Acquisition Mode .
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.14
.15
.16
.16
.16
.16
.17
3. Clock Inputs (IN0, IN1, IN2, IN3/FB_IN) . . . . . . . . . . . . . . . . . . . . . 20
3.1 Input Source Selection . . . .
3.1.1 Manual Input Selection . .
3.1.2 Automatic Input Switching .
3.2 Types of Inputs . . . . . .
3.2.1 Hitless Input Switching . .
3.2.2 Ramped Input Switching .
3.2.3 Glitchless Input Switching .
3.2.4 Unused Inputs. . . . .
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.21
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.25
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.33
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3.3 Fault Monitoring . . . . . . . . . . . . . . . . . .
3.3.1 Input LOS (Loss-of-Signal) Detection . . . . . . . . .
3.3.2 XAXB Reference Clock LOSXAXB (Loss-of-Signal) Detection
3.3.3 Input OOF (Out-of-Frequency) Detection . . . . . . . .
3.3.4 DSPLL Loss-of-Lock (LOL) Detection . . . . . . . . .
3.3.5 Device Status Monitoring . . . . . . . . . . . . .
3.3.6 INTRb Interrupt Configuration . . . . . . . . . . .
4. Output Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.1 Output Crosspoint Switch . . . . . .
4.1.1 Output R Divider Synchronization .
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.37
.38
.39
.40
.40
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4.2 Performance Guidelines for Outputs . . . . . .
4.2.1 Optimizing Output Phase Noise for Si5381/82 .
4.3 Output Signal Format .
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4.4 Output Driver Supply Select .
silabs.com
| Building a more connected world.
Rev. 0.9 | 2
4.5 Differential Outputs . . . . . . . . . . . . . . . . . . . . .
4.5.1 Differential Output Terminations . . . . . . . . . . . . . . .
4.5.2 Differential Output Amplitude Controls. . . . . . . . . . . . .
4.5.3 Differential Output Common Mode Voltage Selection. . . . . . . .
4.5.4 Recommended Settings for Differential LVPECL, LVDS, HCSL, and CML
4.6 LVCMOS Outputs . . . . . . . . . . . . . . . .
4.6.1 LVCMOS Output Terminations . . . . . . . . . .
4.6.2 LVCMOS Output Impedance and Drive Strength Selection.
4.6.3 LVCMOS Output Signal Swing . . . . . . . . . .
4.6.4 LVCMOS Output Polarity . . . . . . . . . . . .
4.7 Output Enable/Disable . . . . . . . . . .
4.7.1 Output Driver State When Disabled . . .
4.7.2 Synchronous Output Enable/Disable Feature
4.7.3 Automatic Output Disable During LOL. . .
4.7.4 Automatic Output Disable During LOSXAXB
4.7.5 Output Driver Disable Source Summary . .
4.8 Output Delay Control (Δt1 – Δt4)
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.42
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5. Zero Delay Mode for DSPLL B . . . . . . . . . . . . . . . . . . . . . . . . 55
6. Digitally Controlled Oscillator (DCO) Mode
. . . . . . . . . . . . . . . . . . . 57
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.57
6.1 Frequency Increment/Decrement Using the Serial Interface
7. Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1 I
2
C Interface .
7.2 SPI Interface .
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59
.61
.63
8. Field Programming
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
. . . . . . . . . . . . . . . . . . . . . . . . . 70
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.70
.71
9. XAXB External References
9.1 Performance of External References .
9.2 Recommended Reference Oscillators .
10. XO and Device Circuit Layout Recommendations
11. Power Management
. . . . . . . . . . . . . . . . 72
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.73
10.1 Si5381/82 64-Pin QFN with External XO Layout Recommendations .
. . . . . . . . . . . . . . . . . . . . . . . . . . . 78
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.78
.78
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11.1 Power Management Features .
11.3 Power Supply Sequencing .
11.4 Grounding Vias .
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11.2 Power Supply Recommendations .
12. Base vs. Factory Preprogrammed Devices . . . . . . . . . . . . . . . . . . . 80
12.1 "Base" Devices (a.k.a. "Blank" Devices).
12.3 Part Numbering Summary .
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.80
.80
.80
12.2 "Factory Preprogrammed" (Custom OPN) Devices .
13. Si5381 Register Map
. . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Rev. 0.9 | 3
silabs.com
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13.1 Page 0 Registers .
13.2 Page 1 Registers .
13.3 Page 2 Registers
13.4 Page 3 Registers
13.5 Page 4 Registers
13.6 Page 5 Registers
13.7 Page 6 Registers
13.8 Page 7 Registers
13.9 Page 9 Registers
13.10 Page A Registers .
13.11 Page B Registers .
13.12 Page C Registers .
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.81
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.128
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. 162
. 164
. 167
14. Si5382 Register Map
14.1 Page 0 Registers
14.2 Page 1 Registers
14.3 Page 2 Registers
14.4 Page 3 Registers
14.5 Page 4 Registers
14.6 Page 5 Registers
14.7 Page 9 Registers
14.8 Page A Registers
14.9 Page B Registers
14.10 Page C Registers .
. . . . . . . . . . . . . . . . . . . . . . . . . . .168
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.168
.185
.191
.198
.201
.212
.222
.224
.226
. 228
15. Appendix—Custom Differential Amplitude Controls
. . . . . . . . . . . . . . .229
16. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
silabs.com
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Rev. 0.9 | 4
Si5381/82 Rev. E Reference Manual
Functional Description
1. Functional Description
The Si5381/82 integrates four/two independent any-frequency DSPLLs in a monolithic IC for applications that require a combination of
4G/LTE, wireline, and general-purpose clocking. Any clock input can be routed to any DSPLL. The output of any DSPLL can be routed
to any of the device clock inputs. Based on 4th generation DSPLL technology, the Si5381/82 provides a clock-tree-on-a-chip solution
for applications that need a mix of 4G/LTE and general-purpose frequencies.
1.1 DSPLL
The DSPLL provides the synthesis for generating the output clock frequencies which are synchronous to the selected input clock fre-
quency or freerun from the reference clock. It consists of a phase detector, a programmable digital loop filter, a high-performance ultra-
low-phase-noise analog VCO, and a user configurable feedback divider. Use of an external XO provides the DSPLL with a stable low-
noise clock source for frequency synthesis and for maintaining frequency accuracy in the Freerun or Holdover modes. No other external
components are required for oscillation. A key feature of DSPLL is providing immunity to external noise coupling from power supplies
and other uncontrolled noise sources that normally exist on printed circuit boards.
The frequency configuration for each of the DSPLLs is programmable through the SPI or I
2
C interface and can also be stored in non-
volatile memory. DSPLLB is primarily used to generate 4G/LTE frequencies. Fractional frequency multiplication (Mn/Md) allows each of
the DSPLLs to lock to any input frequency and generate virtually any output frequency. All divider values for a specific frequency plan
are easily determined using the ClockBuilder Pro utility.
VDD
3
VDDA
Si5381
XTAL
OSC
IN_SEL[1:0]
Si5381
VDDO0
÷R
0A
PD
÷
LPF
M
n_A
M
d_A
OUT0A
OUT0Ab
OUT0
OUT0b
VDDO1
OUT1
OUT1b
VDDO2
OUT2
OUT2b
VDDO3
OUT3
OUT3b
VDDO4
OUT4
OUT4b
VDDO5
OUT5
OUT5b
VDDO6
OUT6
OUT6b
VDDO7
OUT7
OUT7b
VDDO8
OUT8
OUT8b
OUT9
OUT9b
OUT9A
OUT9Ab
VDDO9
÷R
0
÷R
1
÷R
2
÷R
3
÷R
4
DSPLL A
IN0
IN0b
IN1
IN1b
IN2
IN2b
IN3/FB_IN
IN3b/FB_INb
÷P
0
÷P
1
÷P
2
PD
LPF
M
n_B
÷
M
d_B
÷5
÷N
1
÷N
4
DSPLL B
PD
LPF
M
n_C
÷
M
d_C
÷P
3
DSPLL C
÷R
5
÷R
6
PD
÷
LPF
M
n_D
M
d_D
÷R
7
÷R
8
÷R
9
DSPLL D
I2C_SEL
SDA/SDIO
SCLK
A0/CSb
SPI/
I
2
C
NVM
÷R
9A
INTRb
Status
Monitors
PDNb
RSTb
Figure 1.1. Si5381 Block Digram
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