KSZ9567S
7-Port Gigabit Ethernet AVB Switch
with SGMII and RGMII/MII/RMII Interfaces
Highlights
• One port with 10/100/1000 Ethernet MAC
and SGMII interface
• One port with 10/100/1000 Ethernet MAC
and configurable RGMII/MII/RMII interface
• EtherSynch® with full support for IEEE 1588v2
Precision Time Protocol (PTP)
• IEEE 802.1AS/Qav Audio Video Bridging (AVB)
• IEEE 802.1X access control support
• Five ports with integrated 10/100/1000BASE-T PHY
transceivers
• Non-blocking wire-speed Ethernet switching fabric
• Full-featured forwarding and filtering control, includ-
ing Access Control List (ACL) filtering
• Full VLAN and QoS support
• EtherGreen™ power management features,
including low power standby
• Flexible management interface options: SPI, I
2
C,
MIIM, and in-band management via any port
• Industrial temperature range support
• 128-pin TQFP-EP (14 x 14mm) RoHS compliant pkg
• Five Integrated PHY Ports
1000BASE-T/100BASE-TX/10BASE-Te IEEE 802.3
Fast Link-up option significantly reduces link-up time
Auto-negotiation and Auto-MDI/MDI-X support
On-chip termination resistors and internal biasing for
differential pairs to reduce power
- LinkMD® cable diagnostic capabilities for determining
cable opens, shorts, and length
-
-
-
-
• Advanced Switch Capabilities
- IEEE 802.1Q VLAN support for 128 active VLAN
groups and the full range of 4096 VLAN IDs
- IEEE 802.1p/Q tag insertion/removal on per port basis
- VLAN ID on per port or VLAN basis
- IEEE 802.3x full-duplex flow control and half-duplex
back pressure collision control
- IEEE 802.1X access control
(Port-based and MAC address based)
- IGMP v1/v2/v3 snooping for multicast packet filtering
- IPv6 multicast listener discovery (MLD) snooping
- IPv4/IPv6 QoS support, QoS/CoS packet prioritization
- 802.1p QoS packet classification with 4 priority queues
- Programmable rate limiting at ingress/egress ports
• IEEE 1588v2 PTP and Clock Synchronization
-
-
-
-
-
-
-
-
-
-
-
Transparent Clock (TC) with auto correction update
Master and slave Ordinary Clock (OC) support
End-to-end (E2E) or peer-to-peer (P2P)
PTP multicast and unicast message support
PTP message transport over IPv4/v6 and IEEE 802.3
IEEE 1588v2 PTP packet filtering
Synchronous Ethernet support via recovered clock
Compliant with IEEE 802.1BA/AS/Qat/Qav standards
Priority queuing, Low latency cut-through mode
gPTP time synchronization, credit-based traffic shaper
Time aware traffic scheduler per port
Target Applications
•
•
•
•
•
•
Industrial Ethernet (Profinet, MODBUS, Ethernet/IP)
Real-time Ethernet networks
IEC 61850 networks w/ power substation automation
Industrial control/automation switches
Networked measurement and control systems
Test and measurement equipment
• Audio Video Bridging (AVB)
Features
• Switch Management Capabilities
- 10/100/1000Mbps Ethernet switch basic functions:
frame buffer management, address look-up table,
queue management, MIB counters
- Non-blocking store-and-forward switch fabric assures
fast packet delivery by utilizing 4096 entry forwarding
table with 256kByte frame buffer
- Jumbo packet support up to 9000 bytes
- Port mirroring/monitoring/sniffing:
ingress and/or egress traffic to any port
- Rapid spanning tree protocol (RSTP) support for topol-
ogy management and ring/linear recovery
- Multiple spanning tree protocol (MSTP) support
• Comprehensive Configuration Registers Access
- High-speed 4-wire SPI (up to 50MHz), I
2
C interfaces
provide access to all internal registers
- MII Management (MIIM, MDC/MDIO 2-wire) Interface
provides access to all PHY registers
- In-band management via any of the data ports
- I/O pin strapping facility to set certain register bits from
I/O pins at reset time
• Power Management
-
-
-
-
-
Energy detect power-down mode on cable disconnect
Dynamic clock tree control
Unused ports can be individually powered down
Full-chip software power-down
Wake-on-LAN (WoL) standby power mode with PME
interrupt output for system wake upon triggered events
• One External MAC Port with SGMII
• One External MAC Port with RGMII/MII/RMII
- RGMII v2.0, RMII v1.2 with 50MHz reference clock
input/output option, MII in PHY/MAC mode
2017 Microchip Technology Inc.
DS00002393A-page 1
KSZ9567S
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at
docerrors@microchip.com.
We welcome your feedback.
Most Current Documentation
To obtain the most up-to-date version of this documentation, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for cur-
rent devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the
revision of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site;
http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you are
using.
Customer Notification System
Register on our web site at
www.microchip.com
to receive the most current information on all of our products.
DS00002393A-page 2
2017 Microchip Technology Inc.
KSZ9567S
Table of Contents
1.0 Preface ............................................................................................................................................................................................ 4
2.0 Introduction ..................................................................................................................................................................................... 8
3.0 Pin Descriptions and Configuration ................................................................................................................................................. 9
4.0 Functional Description .................................................................................................................................................................. 18
5.0 Device Registers ........................................................................................................................................................................... 63
6.0 Operational Characteristics ......................................................................................................................................................... 203
7.0 Design Guidelines ....................................................................................................................................................................... 220
8.0 Package Information ................................................................................................................................................................... 223
Appendix A: Data Sheet Revision History ......................................................................................................................................... 225
The Microchip Web Site .................................................................................................................................................................... 226
Customer Change Notification Service ............................................................................................................................................. 226
Customer Support ............................................................................................................................................................................. 226
Product Identification System ........................................................................................................................................................... 227
2017 Microchip Technology Inc.
DS00002393A-page 3
KSZ9567S
1.0
1.1
PREFACE
Glossary of Terms
GENERAL TERMS
Description
10 Mbps Ethernet, 2.5V signaling, IEEE 802.3 compliant
100 Mbps Fast Ethernet, IEEE 802.3u compliant
1000 Mbps Gigabit Ethernet, IEEE 802.3ab compliant
Analog-to-Digital Converter
Auto-Negotiation
Audio Video Bridging (IEEE 802.1BA, 802.1AS, 802.1Qat, 802.1Qav)
Baseline Wander
Bridge Protocol Data Unit. Messages which carry the Spanning Tree Protocol informa-
tion.
8 bits
Cyclic Redundancy Check. A common technique for detection data transmission
errors. CRC for Ethernet is 32 bits long.
Control and Status Registers
Destination Address
32 bits
Frame Check Sequence. The extra checksum characters added to the end of an
Ethernet frame, used for error detection and correction.
Frame or Filter ID. Specifies the frame identifier. Alternately is the filter identifier.
First In First Out buffer
Finite State Machine
General Purpose I/O
External system (Includes processor, application software, etc.)
Internet Group Management Protocol. Defined by RFC 1112, RFC 2236, and RFC
4604 to establish multicast group membership in IPv4 networks.
Inter-Packet Gap. A time delay between successive data packets mandated by the
network standard for protocol reasons.
A packet larger than the standard Ethernet packet (1518 bytes). Large packet sizes
allow for more efficient use of bandwidth, lower overhead, less processing, etc.
Least Significant Bit
Least Significant Byte
Media Access Controller. A functional block responsible for implementing the media
access control layer, which is a sublayer of the data link layer.
Medium Dependent Interface. An Ethernet port connection that allows network hubs or
switches to connect to other hubs or switches without a null-modem, or crossover,
cable.
Media Independent Interface with Crossover. An Ethernet port connection that allows
networked end stations (i.e., PCs or workstations) to connect to each other using a
null-modem, or crossover, cable.
Management Information Base. The MIB comprises the management portion of net-
work devices. This can include monitoring traffic levels and faults (statistical), and can
also change operating parameters in network nodes (static forwarding addresses).
Media Independent Interface. The MII accesses PHY registers as defined in the IEEE
802.3 specification.
TABLE 1-1:
Term
10BASE-Te
100BASE-TX
1000BASE-T
ADC
AN
AVB
BLW
BPDU
Byte
CRC
CSR
DA
DWORD
FCS
FID
FIFO
FSM
GPIO
Host
IGMP
IPG
Jumbo Packet
lsb
LSB
MAC
MDI
MDIX
MIB
MII
DS00002393A-page 4
2017 Microchip Technology Inc.
KSZ9567S
TABLE 1-1:
Term
MIIM
MLD
MLT-3
GENERAL TERMS (CONTINUED)
Description
Media Independent Interface Management
Multicast Listening Discovery. This protocol is defined by RFC 3810 and RFC 4604 to
establish multicast group membership in IPv6 networks.
Multi-Level Transmission Encoding (3-Levels). A tri-level encoding method where a
change in the logic level represents a code bit “1” and the logic output remaining at the
same level represents a code bit “0”.
Most Significant Bit
Most Significant Byte
Non Return to Zero. A type of signal data encoding whereby the signal does not return
to a zero state in between bits.
Non Return to Zero Inverted. This encoding method inverts the signal for a “1” and
leaves the signal unchanged for a “0”
Not Applicable
No Connect
Organizationally Unique Identifier
A device or function block which performs the physical layer interface function in a net-
work.
Phase Locked Loop. A electronic circuit that controls an oscillator so that it maintains a
constant phase angle (i.e., lock) on the frequency of an input, or reference, signal.
Precision Time Protocol
Refers to a reserved bit field or address. Unless otherwise noted, reserved bits must
always be zero for write operations. Unless otherwise noted, values are not guaran-
teed when reading reserved bits. Unless otherwise noted, do not read or write to
reserved addresses.
Real-Time Clock
Source Address
Start of Frame Delimiter. The 8-bit value indicating the end of the preamble of an
Ethernet frame.
Signal Quality Error (also known as “heartbeat”)
Start of Stream Delimiter
Transmission Control Protocol
User Datagram Protocol - A connectionless protocol run on top of IP networks
Unshielded Twisted Pair. Commonly a cable containing 4 twisted pairs of wire.
Universally Unique IDentifier
Virtual Local Area Network
16 bits
msb
MSB
NRZ
NRZI
N/A
NC
OUI
PHY
PLL
PTP
RESERVED
RTC
SA
SFD
SQE
SSD
TCP
UDP
UTP
UUID
VLAN
WORD
2017 Microchip Technology Inc.
DS00002393A-page 5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
