PN512
Full NFC Forum-compliant frontend
Rev. 5.2 — 16 June 2016
111352
Product data sheet
COMPANY PUBLIC
1. General description
PN512 is the most broadly adopted NFC frontend - powering more than 10 billion NFC
transactions per year.
It is a highly integrated NFC frontend for contactless communication at 13.56 MHz. This
NFC frontend utilizes an outstanding modulation and demodulation concept completely
integrated for different kinds of contactless communication methods and protocols at
13.56 MHz.
The PN512 NFC frontend supports 4 different operating modes
•
•
•
•
Reader/Writer mode supporting ISO/IEC 14443A/MIFARE and FeliCa scheme
Reader/Writer mode supporting ISO/IEC 14443B
Card Operation mode supporting ISO/IEC 14443A/MIFARE and FeliCa scheme
NFCIP-1 mode
Enabled in Reader/Writer mode for ISO/IEC 14443A/MIFARE, the PN512’s internal
transmitter part is able to drive a reader/writer antenna designed to communicate with
ISO/IEC 14443A/ MIFARE cards and transponders without additional active circuitry. The
receiver part provides a robust and efficient implementation of a demodulation and
decoding circuitry for signals from ISO/IEC 14443A/MIFARE compatible cards and
transponders. The digital part handles the complete ISO/IEC 14443A framing and error
detection (Parity and CRC).
Enabled in Reader/Writer mode for FeliCa, the PN512 NFC frontend supports the FeliCa
communication scheme. The receiver part provides a robust and efficient implementation
of the demodulation and decoding circuitry for FeliCa coded signals. The digital part
handles the FeliCa framing and error detection like CRC. The PN512 supports contactless
communication using FeliCa Higher transfer speeds up to 424 kbit/s in both directions.
The PN512 supports all layers of the ISO/IEC 14443B reader/writer communication
scheme, given correct implementation of additional components, like oscillator, power
supply, coil etc. and provided that standardized protocols, e.g. like ISO/IEC 14443-4
and/or ISO/IEC 14443B anticollision are correctly implemented.
In Card Operation mode, the PN512 NFC frontend is able to answer to a reader/writer
command either according to the FeliCa or ISO/IEC 14443A/MIFARE card interface
scheme. The PN512 generates the digital load modulated signals and in addition with an
external circuit the answer can be sent back to the reader/writer. A complete card
functionality is only possible in combination with a secure IC using the S
2
C interface.
NXP Semiconductors
PN512
Full NFC Forum-compliant frontend
Additionally, the PN512 NFC frontend offers the possibility to communicate directly to an
NFCIP-1 device in the NFCIP-1 mode. The NFCIP-1 mode offers different communication
mode and transfer speeds up to 424 kbit/s according to the Ecma 340 and ISO/IEC 18092
NFCIP-1 Standard. The digital part handles the complete NFCIP-1 framing and error
detection.
Various host controller interfaces are implemented:
•
•
•
•
8-bit parallel interface
1
SPI interface
serial UART (similar to RS232 with voltage levels according pad voltage supply)
I
2
C interface.
1.1 Different available versions
The PN512 is available in three versions:
•
PN5120A0HN1/C2 (HVQFN32), PN5120A0HN/C2 (HVQFN40) and PN5120A0ET/C2
(TFBGA64), hereafter named as version 2.0
•
PN512AA0HN1/C2 (HVQFN32) and PN512AA0HN1/C2BI (HVQFN32 with Burn In),
hereafter named as industrial version, fulfilling the automotive qualification stated in
AEC-Q100 grade 3 from the Automotive Electronics Council, defining the critical
stress test qualification for automotive integrated circuits (ICs).
The customer recognizes that:
–
since the product was not originally designed for automotive use, it will not be
possible to achieve the levels of quality and failure analysis that are normally
associated with products explicitly designed for automotive use.
–
the product qualification conforms to AEC-Q100.
–
all product production locations are certified according to TS16949.
•
PN5120A0HN1/C1(HVQFN32) and PN5120A0HN/C1 (HVQFN40), hereafter named
as version 1.0
The data sheet describes the functionality for the industrial version and version 2.0. The
differences of the version 1.0 to the version 2.0 are summarized in
Section 20.
The
industrial version has only differences within the outlined characteristics and limitations.
1.
PN512
8-bit parallel Interface only available in HVQFN40 package.
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 5.2 — 16 June 2016
111352
2 of 137
NXP Semiconductors
PN512
Full NFC Forum-compliant frontend
2. Features and benefits
Includes NXP ISO/IEC14443-A, Innovatron ISO/IEC14443-B and NXP MIFARE
Crypto 1 intellectual property
licensing rights
Fast and cost-efficient NFC design startup
Highly integrated analog circuitry to demodulate and decode responses
Buffered output drivers for connecting an antenna with the minimum number of
external components
Integrated RF Level detector
Integrated data mode detector
Supports ISO/IEC 14443 A/MIFARE
Supports ISO/IEC 14443 B Read/Write modes
Typical operating distance in Read/Write mode up to 50 mm depending on the
antenna size and tuning
Typical operating distance in NFCIP-1 mode up to 50 mm depending on the antenna
size and tuning and power supply
Typical operating distance in ISO/IEC 14443A/MIFARE card or FeliCa Card Operation
mode of about 100 mm depending on the antenna size and tuning and the external
field strength
Supports MIFARE Classic encryption in Reader/Writer mode
ISO/IEC 14443A higher transfer speed communication at 212 kbit/s and 424 kbit/s
Contactless communication according to the FeliCa scheme at 212 kbit/s and
424 kbit/s
Integrated RF interface for NFCIP-1 up to 424 kbit/s
S
2
C interface
Additional power supply to directly supply the smart card IC connected via S
2
C
Supported host interfaces
SPI up to 10 Mbit/s
I
2
C-bus interface up to 400 kBd in Fast mode, up to 3400 kBd in High-speed mode
RS232 Serial UART up to 1228.8 kBd, with voltage levels dependant on pin
voltage supply
8-bit parallel interface with and without Address Latch Enable
FIFO buffer handles 64 byte send and receive
Flexible interrupt modes
Hard reset with low power function
Power-down mode per software
Programmable timer
Internal oscillator for connection to 27.12 MHz quartz crystal
2.5 V to 3.6 V power supply
CRC coprocessor
Programmable I/O pins
Internal self-test
PN512
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 5.2 — 16 June 2016
111352
3 of 137
NXP Semiconductors
PN512
Full NFC Forum-compliant frontend
3. Quick reference data
Table 1.
Symbol
V
DDA
V
DDD
Quick reference data
Parameter
analog supply voltage
digital supply voltage
Conditions
V
DD(PVDD)
V
DDA
= V
DDD
= V
DD(TVDD)
;
V
SSA
= V
SSD
= V
SS(PVSS)
= V
SS(TVSS)
= 0 V
[1][2]
Min
2.5
Typ
-
Max
3.6
Unit
V
V
DD(TVDD)
TVDD supply voltage
V
DD(PVDD)
PVDD supply voltage
V
DD(SVDD)
SVDD supply voltage
I
pd
power-down current
V
SSA
= V
SSD
= V
SS(PVSS)
= V
SS(TVSS)
= 0 V
V
DDA
= V
DDD
= V
DD(TVDD)
= V
DD(PVDD)
= 3 V
hard power-down; pin NRSTPD set LOW
soft power-down; RF level detector on
I
DDD
I
DDA
digital supply current
analog supply current
pin DVDD; V
DDD
= 3 V
pin AVDD; V
DDA
= 3 V, CommandReg register’s
RcvOff bit = 0
pin AVDD; receiver switched off; V
DDA
= 3 V,
CommandReg register’s RcvOff bit = 1
I
DD(PVDD)
I
DD(TVDD)
T
amb
I
pd
PVDD supply current
TVDD supply current
ambient temperature
power-down current
pin PVDD
pin TVDD; continuous wave
HVQFN32, HVQFN40, TFBGA64
V
DDA
= V
DDD
= V
DD(TVDD)
= V
DD(PVDD)
= 3 V
hard power-down; pin NRSTPD set LOW
soft power-down; RF level detector on
T
amb
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[4]
[4]
[5]
[6][7][8]
[4]
[4]
[3]
1.6
1.6
-
-
-
-
-
-
-
30
-
-
-
-
6.5
7
3
-
60
3.6
3.6
5
10
9
10
5
40
100
+85
V
V
A
A
mA
mA
mA
mA
mA
C
lndustrial version PN512AA0HN1:
-
-
40
-
-
-
15
30
+90
A
A
C
ambient temperature
HVQFN32
Supply voltages below 3 V reduce the performance in, for example, the achievable operating distance.
V
DDA
, V
DDD
and V
DD(TVDD)
must always be the same voltage.
V
DD(PVDD)
must always be the same or lower voltage than V
DDD
.
I
pd
is the total current for all supplies.
I
DD(PVDD)
depends on the overall load at the digital pins.
I
DD(TVDD)
depends on V
DD(TVDD)
and the external circuit connected to pins TX1 and TX2.
During typical circuit operation, the overall current is below 100 mA.
Typical value using a complementary driver configuration and an antenna matched to 40
between pins TX1 and TX2 at 13.56 MHz.
PN512
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 5.2 — 16 June 2016
111352
4 of 137
NXP Semiconductors
PN512
Full NFC Forum-compliant frontend
4. Ordering information
Table 2.
Ordering information
Package
Name
PN5120A0HN1/C2
PN5120A0HN/C2
PN512AA0HN1/C2
PN512AA0HN1/C2BI
PN5120A0HN1/C1
PN5120A0HN/C1
PN5120A0ET/C2
HVQFN32
HVQFN40
HVQFN32
HVQFN32
HVQFN32
HVQFN40
TFBGA64
Description
plastic thermal enhanced very thin quad flat package; no leads;
32 terminal; body 5
5
0.85 mm
plastic thermal enhanced very thin quad flat package; no leads;
40 terminals; body 6
6
0.85 mm
plastic thermal enhanced very thin quad flat package; no leads;
32 terminal; body 5
5
0.85 mm
plastic thermal enhanced very thin quad flat package; no leads;
32 terminal; body 5
5
0.85 mm
plastic thermal enhanced very thin quad flat package; no leads;
32 terminal; body 5
5
0.85 mm
plastic thermal enhanced very thin quad flat package; no leads;
40 terminals; body 6
6
0.85 mm
plastic thin fine-pitch ball grid array package; 64 balls
Version
SOT617-1
SOT618-1
SOT617-1
SOT617-1
SOT617-1
SOT618-1
SOT1336-1
Type number
PN512
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 5.2 — 16 June 2016
111352
5 of 137
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
