MC14536B
Programmable Timer
The MC14536B programmable timer is a 24−stage binary ripple
counter with 16 stages selectable by a binary code. Provisions for an
on−chip RC oscillator or an external clock are provided. An on−chip
monostable circuit incorporating a pulse−type output has been
included. By selecting the appropriate counter stage in conjunction
with the appropriate input clock frequency, a variety of timing can be
achieved.
Features
http://onsemi.com
•
•
•
•
•
•
•
•
•
•
•
•
•
24 Flip−Flop Stages − Will Count From 2
0
to 2
24
Last 16 Stages Selectable By Four−Bit Select Code
8−Bypass Input Allows Bypassing of First Eight Stages
Set and Reset Inputs
Clock Inhibit and Oscillator Inhibit Inputs
On−Chip RC Oscillator Provisions
On−Chip Monostable Output Provisions
Clock Conditioning Circuit Permits Operation with Very Long Rise
and Fall Times
Test Mode Allows Fast Test Sequence
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load over the Rated Temperature Range
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
1
SOIC−16 WB
DW SUFFIX
CASE 751G
1
SOEIAJ−16
F SUFFIX
CASE 966
1
TSSOP−16
DT SUFFIX
CASE 948F
PIN ASSIGNMENT
SET
RESET
IN 1
OUT 1
OUT 2
8−BYPASS
CLOCK INH
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
MONO−IN
OSC INH
DECODE
D
C
B
A
MARKING DIAGRAMS
16
MAXIMUM RATINGS
(Voltages Referenced to V
SS
)
Rating
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Input or Output Current
(DC or Transient) per Pin
Power Dissipation per Package (Note 1)
Ambient Temperature Range
Storage Temperature Range
Lead Temperature, (8−Second Soldering)
Symbol
V
DD
V
in
,
V
out
I
in
, I
out
P
D
T
A
T
stg
T
L
Value
−0.5 to +18.0
−0.5 to V
DD
+ 0.5
±10
500
−55 to +125
−65 to +150
260
Unit
V
V
1
mA
mW
°C
°C
°C
1
SOIC−16 WB
14536B
AWLYWWG
14
536B
ALYWG
G
1
TSSOP−16
MC14536B
ALYWG
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C from 65_C to 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
≤
(V
in
or V
out
)
≤
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V
SS
or V
DD
). Unused outputs must be left open.
SOEIAJ−16
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
G or
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
©
Semiconductor Components Industries, LLC, 2014
1
November, 2014 − Rev. 14
Publication Order Number:
MC14536B/D
MC14536B
CLOCK INH.
7
OSC. INHIBIT 14
RESET SET 8 BYPASS
2
1 6
IN
1
3
4
OUT
1
5
OUT
2
STAGES
1 THRU 8
STAGES 9 THRU 24
Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
A 9
B 10
C 11
D 12
DECODER
V
DD
= PIN 16
V
SS
= PIN 8
MONO-IN 15
MONOSTABLE
MULTIVIBRATOR
13
DECODE
OUT
Figure 1. Block Diagram
FUNCTION TABLE
Clock
Inh
0
0
0
0
1
0
0
0
OSC
Inh
0
0
0
0
0
1
X
0
0
−
0
0
1
1
−
1
1
Decode
Out
No
Change
Advance to
next state
1
0
No
Change
No
Change
No
Change
Advance to
next state
In
1
Set
0
0
Reset
0
0
0
1
0
0
0
0
Out 1
Out 2
X
X
X
X
0
1
1
0
0
0
0
0
X = Don’t Care
http://onsemi.com
2
MC14536B
ELECTRICAL CHARACTERISTICS
(Voltages Referenced to V
SS
)
− 55_C
Characteristic
Output Voltage
V
in
= V
DD
or 0
“0” Level
Symbol
V
OL
V
DD
Vdc
5.0
10
15
5.0
10
15
5.0
10
15
“1” Level
(V
O
= 0.5 or 4.5 Vdc)
(V
O
= 1.0 or 9.0 Vdc)
(V
O
= 1.5 or 13.5 Vdc)
Output Drive Current
(V
OH
= 2.5 Vdc)
(V
OH
= 4.6 Vdc)
(V
OH
= 9.5 Vdc)
(V
OH
= 13.5 Vdc)
(V
OH
= 2.5 Vdc)
(V
OH
= 4.6 Vdc)
(V
OH
= 9.5 Vdc)
(V
OH
= 13.5 Vdc)
(V
OL
= 0.4 Vdc)
(V
OL
= 0.5 Vdc)
(V
OL
= 1.5 Vdc)
Input Current
Input Capacitance
(V
in
= 0)
Quiescent Current (Per Package)
I
OH
Source
Pins 4 & 5
5.0
5.0
10
15
5.0
5.0
10
15
I
OL
5.0
10
15
15
−
5.0
10
15
5.0
10
15
–1.2
–0.25
–0.62
–1.8
–3.0
–0.64
–1.6
–4.2
0.64
1.6
4.2
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
±0.1
−
5.0
10
20
–1.0
–0.25
–0.5
–1.5
–2.4
–0.51
–1.3
–3.4
0.51
1.3
3.4
−
−
−
−
−
–1.7
–0.36
–0.9
–3.5
–4.2
–0.88
–2.25
–8.8
0.88
2.25
8.8
±0.00001
5.0
0.010
0.020
0.030
−
−
−
−
−
−
−
−
−
−
−
±0.1
7.5
5.0
10
20
–0.7
–0.14
–0.35
–1.1
–1.7
–0.36
–0.9
–2.4
0.36
0.9
2.4
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
±1.0
−
150
300
600
mAdc
V
IH
5.0
10
15
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
mAdc
Min
−
−
−
4.95
9.95
14.95
−
−
−
Max
0.05
0.05
0.05
−
−
−
1.5
3.0
4.0
Min
−
−
−
4.95
9.95
14.95
−
−
−
25_C
Typ
(Note 2)
0
0
0
5.0
10
15
2.25
4.50
6.75
Max
0.05
0.05
0.05
−
−
−
1.5
3.0
4.0
125_C
Min
−
−
−
4.95
9.95
14.95
−
−
−
Max
0.05
0.05
0.05
−
−
−
1.5
3.0
4.0
Vdc
Unit
Vdc
“1” Level
V
in
= 0 or V
DD
Input Voltage
(V
O
= 4.5 or 0.5 Vdc)
(V
O
= 9.0 or 1.0 Vdc)
(V
O
= 13.5 or 1.5 Vdc)
“0” Level
V
OH
Vdc
V
IL
Vdc
Source
Pin 13
Sink
mAdc
I
in
C
in
I
DD
mAdc
pF
mAdc
Total Supply Current (Note 3, 4)
(Dynamic plus Quiescent,
Per Package)
(C
L
= 50 pF on all outputs, all
buffers switching)
I
T
I
T
= (1.50
mA/kHz)
f + I
DD
I
T
= (2.30
mA/kHz)
f + I
DD
I
T
= (3.55
mA/kHz)
f + I
DD
mAdc
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF:
I
T
(C
L
) = I
T
(50 pF) + (C
L
– 50) Vfk
where: I
T
is in
mA
(per package), C
L
in pF, V = (V
DD
– V
SS
) in volts, f in kHz is input frequency, and k = 0.003.
http://onsemi.com
3
MC14536B
SWITCHING CHARACTERISTICS
(Note 5) (C
L
= 50 pF, T
A
= 25_C)
Characteristic
Output Rise and Fall Time (Pin 13)
t
TLH
, t
THL
= (1.5 ns/pF) C
L
+ 25 ns
t
TLH
, t
THL
= (0.75 ns/pF) C
L
+ 12.5 ns
t
TLH
, t
THL
= (0.55 ns/pF) C
L
+ 9.5 ns
Propagation Delay Time
Clock to Q1, 8−Bypass (Pin 6) High
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 1715 ns
t
PLH
, t
PHL
= (0.66 ns/pF) C
L
+ 617 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 425 ns
Clock to Q1, 8−Bypass (Pin 6) Low
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 3715 ns
t
PLH
, t
PHL
= (0.66 ns/pF) C
L
+ 1467 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 1075 ns
Clock to Q16
t
PHL
, t
PLH
= (1.7 ns/pF) C
L
+ 6915 ns
t
PHL
, t
PLH
= (0.66 ns/pF) C
L
+ 2967 ns
t
PHL
, t
PLH
= (0.5 ns/pF) C
L
+ 2175 ns
Reset to Q
n
t
PHL
= (1.7 ns/pF) C
L
+ 1415 ns
t
PHL
= (0.66 ns/pF) C
L
+ 567 ns
t
PHL
= (0.5 ns/pF) C
L
+ 425 ns
Clock Pulse Width
Symbol
t
TLH
,
t
THL
V
DD
5.0
10
15
Min
−
−
−
Typ
(Note 6)
100
50
40
Max
200
100
80
ns
5.0
10
15
t
PLH
,
t
PHL
5.0
10
15
5.0
10
15
5.0
10
15
t
WH
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
1000
400
300
−
−
−
−
−
−
−
−
−
−
−
−
600
200
170
−
−
−
1800
650
450
3.8
1.5
1.1
7.0
3.0
2.2
1500
600
450
300
100
85
1.2
3.0
5.0
No Limit
500
200
150
−
−
−
ns
3600
1300
1000
ms
7.6
3.0
2.3
ms
14
6.0
4.5
ns
3000
1200
900
−
−
−
0.4
1.5
2.0
ns
Unit
ns
t
PLH
,
t
PHL
t
PLH
,
t
PHL
t
PHL
Clock Pulse Frequency (50% Duty Cycle)
f
cl
MHz
Clock Rise and Fall Time
t
TLH
,
t
THL
t
WH
−
Reset Pulse Width
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
http://onsemi.com
4
MC14536B
PIN DESCRIPTIONS
INPUTS
SET (Pin 1)
− A high on Set asynchronously forces Decode
Out to a high level. This is accomplished by setting an output
conditioning latch to a high level while at the same time
resetting the 24 flip−flop stages. After Set goes low (inactive),
the occurrence of the first negative clock transition on IN
1
causes Decode Out to go low. The counter’s flip−flop stages
begin counting on the second negative clock transition of IN
1
.
When Set is high, the on−chip RC oscillator is disabled. This
allows for very low−power standby operation.
RESET (Pin 2)
− A high on Reset asynchronously forces
Decode Out to a low level; all 24 flip−flop stages are also reset
to a low level. Like the Set input, Reset disables the on−chip
RC oscillator for standby operation.
IN
1
(Pin 3)
− The device’s internal counters advance on the
negative−going edge of this input. IN
1
may be used as an
external clock input or used in conjunction with OUT
1
and
OUT
2
to form an RC oscillator. When an external clock is
used, both OUT
1
and OUT
2
may be left unconnected or used
to drive 1 LSTTL or several CMOS loads.
8−BYPASS (Pin 6)
− A high on this input causes the first 8
flip−flop stages to be bypassed. This device essentially
becomes a 16−stage counter with all 16 stages selectable.
Selection is accomplished by the A, B, C, and D inputs. (See
the truth tables.)
CLOCK INHIBIT (Pin 7)
− A high on this input
disconnects the first counter stage from the clocking source.
This holds the present count and inhibits further counting.
However, the clocking source may continue to run.
Therefore, when Clock Inhibit is brought low, no oscillator
startup time is required. When Clock Inhibit is low, the
counter will start counting on the occurrence of the first
negative edge of the clocking source at IN
1
.
OSC INHIBIT (Pin 14)
− A high level on this pin stops the
RC oscillator which allows for very low−power standby
operation. May also be used, in conjunction with an external
clock, with essentially the same results as the Clock Inhibit
input.
MONO−IN (Pin 15)
− Used as the timing pin for the
on−chip monostable multivibrator. If the Mono−In input is
connected to V
SS
, the monostable circuit is disabled, and
Decode Out is directly connected to the selected Q output.
The monostable circuit is enabled if a resistor is connected
between Mono−In and V
DD
. This resistor and the device’s
internal capacitance will determine the minimum output
pulse widths. With the addition of an external capacitor to
V
SS
, the pulse width range may be extended. For reliable
operation the resistor value should be limited to the range of
5 kW to 100 kW and the capacitor value should be limited to
a maximum of 1000 pf. (See figures 4, 5, 6, and 11).
A, B, C, D (Pins 9, 10, 11, 12)
− These inputs select the
flip−flop stage to be connected to Decode Out. (See the truth
tables.)
OUTPUTS
OUT
1
, OUT
2
(Pin 4, 5)
− Outputs used in conjunction with
IN
1
to form an RC oscillator. These outputs are buffered and
may be used for 2
0
frequency division of an external clock.
DECODE OUT (Pin 13)
− Output function depends on
configuration. When the monostable circuit is disabled, this
output is a 50% duty cycle square wave during free run.
TEST MODE
The test mode configuration divides the 24 flip−flop
stages into three 8−stage sections to facilitate a fast test
sequence. The test mode is enabled when 8−Bypass, Set and
Reset are at a high level. (See Figure 9.)
TRUTH TABLES
Input
8−Bypass
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
C
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Stage Selected
for Decode Out
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Input
8−Bypass
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
C
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Stage Selected
for Decode Out
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
http://onsemi.com
5
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
