Low Skew, 1-to-4, Differential-to-HSTL
Fanout Buffer
8523
DATA SHEET
General Description
The 8523 is a low skew, high performance 1-to-4
Differential-to-HSTL Fanout Buffer. The 8523 has two selectable
clock inputs. The CLK, nCLK pair can accept most standard
differential input levels. The PCLK, nPCLK pair can accept LVPECL,
CML, or SSTL input levels. The clock enable is internally
synchronized to eliminate runt pulses on the outputs during
asynchronous assertion/deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics make the
8523 ideal for those applications demanding well defined
performance and repeatability.
Features
•
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•
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Four differential output HSTL compatible outputs
Selectable differential CLK, nCLK or LVPECL clock inputs
CLK, nCLK pair can accept the following differential input levels:
LVPECL, LVDS, HSTL, HCSL, SSTL
PCLK, nPCLK pair can accept the following differential input
levels: LVPECL, CML, SSTL
Maximum output frequency: 650MHz
Translates any single-ended input signal to HSTL levels with
resistor bias on nCLK input
Additive phase jitter, RMS: 0.082ps (typical), 100MHz f
OUT
Additive phase jitter, RMS: 0.190ps (typical), 120MHz f
OUT
Output skew: 30ps (maximum)
Part-to-part skew: 200ps (maximum)
3.3V core, 1.8V output operating supply
0°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
CLK_EN
Pullup
D
Q
CLK
Pulldown
nCLK
Pullup
PCLK
Pulldown
nPCLK
Pullup
CLK_SEL
Pulldown
LE
0
1
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q0
nQ0
Pin Assignment
GND
CLK_EN
CLK_SEL
CLK
nCLK
PCLK
nPCLK
nc
nc
V
DD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q0
nQ0
V
DDO
Q1
nQ1
Q2
nQ2
V
DDO
Q3
nQ3
8523
20-Lead TSSOP
6.5mm x 4.4mm x 0.925mm package body
G Package
Top View
8523 Rev E 6/15/15
1
©2015 Integrated Device Technology, Inc.
8523 DATA SHEET
Table 1. Pin Descriptions
Number
1
2
Name
GND
CLK_EN
Power
Input
Pullup
Type
Description
Power supply ground.
Synchronizing clock enable. When HIGH, clock outputs follow clock input.
When LOW, Qx outputs are forced low, nQx outputs are forced high.
LVCMOS / LVTTL interface levels.
Clock select input. When HIGH, selects differential PCLK, nPCLK inputs. When
LOW, selects CLK, nCLK inputs. LVCMOS / LVTTL interface levels.
Non-inverting differential clock input.
Inverting differential clock input.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input.
No connect.
Positive supply pin.
Differential output pair. HSTL interface levels.
Output supply pins.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
3
4
5
6
7
8, 9
10
11, 12
13, 18
14, 15
16, 17
19, 20
CLK_SEL
CLK
nCLK
PCLK
nPCLK
nc
V
DD
nQ3, Q3
V
DDO
nQ2, Q2
nQ1, Q1
nQ0, Q0
Input
Input
Input
Input
Input
Unused
Power
Output
Power
Output
Output
Output
Pulldown
Pulldown
Pullup
Pulldown
Pullup
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-HSTL FANOUT BUFFER
2
Rev E 6/15/15
8523 DATA SHEET
Function Tables
Table 3A. Control Input Function Table
Inputs
CLK_EN
0
0
1
1
CLK_SEL
0
1
0
1
Selected Source
CLK, nCLK
PCLK, nPCLK
CLK, nCLK
PCLK, nPCLK
Q[0:3]
Disabled; LOW
Disabled; LOW
Enabled
Enabled
Outputs
nQ[0:3]
Disabled; HIGH
Disabled; HIGH
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK, nCLK and PCLK, nPCLK inputs as described in Table 3B.
Disabled
nCLK, nPCLK
CLK, PCLK
Enabled
CLK_EN
nQ[0:3]
Q[0:3]
Figure 1. CLK_EN Timing Diagram
Table 3B. Clock Input Function Table
Inputs
CLK or PCLK
0
1
0
1
Biased; NOTE 1
Biased; NOTE 1
nCLK or nPCLK
0
1
Biased; NOTE 1
Biased; NOTE 1
0
1
Q[0:3]
LOW
HIGH
LOW
HIGH
HIGH
LOW
Outputs
nQ[0:3]
HIGH
LOW
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Differential
Differential to Differential
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Polarity
Non-Inverting
Non-Inverting
Non-Inverting
Non-Inverting
Inverting
Inverting
Rev E 6/15/15
3
LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-HSTL FANOUT BUFFER
8523 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DDO
+ 0.5V
73.2C/W (0 lfpm)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= 3.3V ± 5%, V
DDO
= 1.8V ±0.2V, T
A
= 0°C to 70°C
Symbol
V
DD
V
DDO
I
DD
Parameter
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
1.6
Typical
3.3
1.8
Maximum
3.465
2.0
50
Units
V
V
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
DD
= 3.3V ± 5%, V
DDO
= 1.8V ±0.2V, T
A
= 0°C to 70°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
CLK_EN
Input High Current
CLK_SEL
CLK_EN
I
IL
Input Low Current
CLK_SEL
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-150
-5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
5
150
Units
V
V
µA
µA
µA
µA
Table 4C. Differential DC Characteristics,
V
DD
= 3.3V ± 5%, V
DDO
= 1.8V ±0.2V, T
A
= 0°C to 70°C
Symbol
I
IH
Parameter
nCLK
Input High Current
CLK
nCLK
I
IL
V
PP
V
CMR
Input Low Current
CLK
Peak-to-Peak Voltage; NOTE 1
Common Mode Input Voltage; NOTE 1, 2
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-150
-5
0.15
0.5
1.3
V
DD
– 0.85
Minimum
Typical
Maximum
5
150
Units
µA
µA
µA
µA
V
V
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as V
IH
.
LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-HSTL FANOUT BUFFER
4
Rev E 6/15/15
8523 DATA SHEET
Table 4D. LVPECL DC Characteristics,
V
DD
= 3.3V ± 5%, V
DDO
= 1.8V ±0.2V, T
A
= 0°C to 70°C
Symbol
I
IH
Parameter
nPCLK
Input High Current
PCLK
nPCLK
I
IL
V
PP
V
CMR
Input Low Current
PCLK
Peak-to-Peak Voltage
Common Mode Input Voltage; NOTE 1
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-150
-5
0.3
1.5
1.0
V
DD
Minimum
Typical
Maximum
5
150
Units
µA
µA
µA
µA
V
V
NOTE 1: Common mode input voltage is defined as V
IH
.
Table 4E. HSTL DC Characteristics,
V
DD
= 3.3V ± 5%, V
DDO
= 1.8V ±0.2V, T
A
= 0°C to 70°C
Symbol
V
OH
V
OL
V
OX
V
SWING
Parameter
Output High Current;
NOTE 1
Output Low Current;
NOTE 1
Output
Crossover Voltage
Peak-to-Peak
Output Voltage Swing
Test Conditions
Minimum
0.9
0
40% x (V
OH
– V
OL
) + V
OL
0.75
Typical
Maximum
1.4
0.4
60% x (V
OH
– V
OL
) + V
OL
1.25
Units
V
V
V
V
NOTE 1: Outputs termination with 50 to ground.
AC Electrical Characteristics
Table 5. AC Characteristics,
V
DD
= 3.3V ± 5%, V
DDO
= 1.8V ±0.2V, T
A
= 0°C to 70°C
Symbol
f
OUT
t
PD
Parameter
Output Frequency
Propagation Delay; NOTE 1
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
Output Skew; NOTE 2, 3
Part-to-Part Skew; NOTE 3, 4
Output Rise/Fall Time
Output Duty Cycle
20% to 80% @ 50MHz
250
45
ƒ
650MHz
f
OUT
= 100MHz,
Integration Range: 12kHz - 20MHz
f
OUT
= 120MHz,
Integration Range: 12kHz - 20MHz
1.0
0.082
0.190
30
200
700
55
Test Conditions
Minimum
Typical
Maximum
650
1.6
Units
MHz
ns
ps
ps
ps
ps
ps
%
tjit
tsk(o)
tsk(pp)
t
R
/ t
F
odc
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters measured at 500MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at output differential cross
points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
Rev E 6/15/15
5
LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-HSTL FANOUT BUFFER
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