SiC645, SiC645A
www.vishay.com
Vishay Siliconix
60 A VRPower
®
Smart Power Stage (SPS) Module with Integrated
High Accuracy Current and Temperature Monitors
FEATURES
• Input range: 4.5 V to 18 V
• Supports 60 A DC current
• Compatible with 3.3 V (SiC645A) and 5 V
(SiC645) tri-state PWM
• Down slope current sensing
• ± 3 % accuracy current monitor (I
MON
) with REF
IN
input
• 8 mV/°C temperature monitor with OT flag
DESCRIPTION
The SiC645 is a smart VRPower
®
device that integrates a
high side and low side MOSFET, a high performance driver
with integrated bootstrap FET. The SiC645 offers high
accuracy current and temperature monitors that can be fed
back to the controller and doubler to complete a multiphase
DC/DC system. They simplify design and increase
performance by eliminating the DCR sensing network and
associated thermal compensation. Light-load efficiency is
supported via a dedicated left control pin. An industry
leading thermally enhanced dual cooled, 5 mm x 5 mm
PowerPAK
®
MLP package allows minimal overall PCB real
estate and low profile construction.
The devices feature a 3.3 V (SiC645A) or 5 V (SiC645)
compatible tri-state PWM input that, working together with
multiphase PWM controllers, will provide a robustsolution in
the event of abnormal operating conditions. The SiC645
also improves system performance and reliability with
integrated fault protection of UVLO, over-temperature and
over-current. An open-drain fault reporting pin simplifies the
handshake between the smart VRPower device and
multiphase controllers and can be used to disable the
controller during start-up and fault conditions.
• Dedicated low side FET control input
• Fault protection
- High side FET short and over-current protection
- Over-temperature protection
- V
CC
and V
IN
under voltage lockout (UVLO)
• Open drain fault reporting output
• Up to 2 MHz switching frequency
• Material categorization: for definitions of compliance
please see
www.vishay.com/doc?99912
APPLICATIONS
•
•
•
•
High frequency and high efficiency VRM and VRD
Core, graphic, and memory regulators for microprocessors
High density VR for server, networking, and cloud computing
POL DC/DC converters and video gaming consoles
TYPICAL APPLICATION DIAGRAM
+12 V
+5 V
PV
CC
BOOT
PHASE
V
CC
V
IN
V
CC
LGCTRL
PWM
CS#n
CSRTN#n
Multiphase
controller
TEMP
EN
PWM
IMON
REF
IN
TMON
FAULT#
Smart
control
Shoot-
through
protection
L
OUT
SW
PV
CC
V
OUT
C
OUT
GND
GND
SiC645
Fig. 1 - Typical Application Block Diagram
S20-0486-Rev. C, 29-Jun-2020
Document Number: 65424
1
For technical questions, contact:
powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
GND
SiC645, SiC645A
www.vishay.com
TYPICAL APPLICATION CIRCUIT WITH SiC645
Vishay Siliconix
+3.3 V
V
CCS
V
CCS
V
CC
5V
5V
V
CC
SiC645
PV
CC
V
IN
BOOT
PHASE
SW
GND
5V
V
IN
LGCTRL
FAULT#
TMON
PWM
IMON
REF
IN
VSENV
CORE
RGNDV
CORE
ENV
CORE
PGV
CORE
TEMPVCORE
PWM1
CS1
CSRTN1
Multiphase
controller
SVDATA
SVCLK
nSVALERT
nVRHOT
nPINALERT
PWM3-5
PMSDA
PMSCL
nPMALERT
CS3-5
CSRTN3-5
PWM2
CS2
CSRTN2
5V
5V
V
CC
SiC645
PV
CC
V
IN
5V
V
IN
V
CORE
LGCTRL
FAULT# BOOT
TMON PHASE
PWM
IMON
REF
IN
GND
SW
N phases
5V
5V
CFP
V
CC
SiC645
PV
CC
V
IN
5V
V
IN
LGCTRL
FAULT# BOOT
TMON PHASE
PWM6
CS6
CSRTN6
PWM
IMON
REF
IN
GND
SW
V
IN
V
INSEN
5V
5V
PGV
SA
ENV
SA
RGNDV
SA
VSENV
SA
TEMPV
SA
PWMV
SA
CSV
SA
CSRTNV
SA
V
CC
SiC645
PV
CC
V
IN
5V
V
IN
LGCTRL
FAULT# BOOT
TMON PHASE
PWM
IMON
REF
IN
GND
V
SA
V
CCS
SW
GND
ADDRESS
CONFIG
Fig. 2 - Typical Application Circuit
S20-0486-Rev. C, 29-Jun-2020
Document Number: 65424
2
For technical questions, contact:
powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiC645, SiC645A
www.vishay.com
Vishay Siliconix
+3.3 V
V
CCS
5V
5V
V
CC
SiC645
PV
CC
V
IN
BOOT
PHASE
SW
GND
5V
V
IN
LGCTRL
PWM
IMON
REF
IN
V
CCS
V
CC
Phase doubler
PWMA
CSENA
CSRTNA
PWM1
PWM
CSRTNB
CSENB
PWMB
5V
5V
CS1
CSRTN1
TMON
FAULT#
VSENV
CORE
RGNDV
CORE
V
CC
SiC645
PV
CC
V
IN
BOOT
PHASE
SW
GND
5V
V
IN
Digital
multiphase
LGCTRL
PWM
IMON
REF
IN
TMON
FAULT#
Load
PWM2-5
CS2-5
CSRTN2-5
N Phases
TEMPV
CORE
ENV
CORE
5V
5V
V
CC
SiC645
PV
CC
V
IN
BOOT
PHASE
SW
GND
5V
V
IN
LGCTRL
PWM
IMON
REF
IN
Phase doubler
PWMA
CSENA
CSRTNA
PWM
CSRTNB
CSENB
PWMB
5V
5V
CS6
CSRTN6
V
CCS
TMON
FAULT#
PWM6
ISL99227B
V
CC
PV
CC
LGCTRL
PWM
IMON
REF
IN
TMON
FAULT#
GND
V
IN
BOOT
PHASE
SW
5V
V
IN
Fig. 3 - Typical Application Circuit
S20-0486-Rev. C, 29-Jun-2020
Document Number: 65424
3
For technical questions, contact:
powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiC645, SiC645A
www.vishay.com
FUNCTIONAL BLOCK DIAGRAM
PV
CC
PHASE
BOOT
V
IN
V
IN
UVLO
BOOT
switch
control
2.5 V
V
CC
UVLO
V
CCPOR
V
UGH
33.5K (for 3.3 V)
16.5K (for 5.0 V)
PWM
16.5K
V
LGH
HFET
short
PWML
100 mV
+
-
+
-
V
CC
-BOOT level
shifter
PWM
logic
HS
driver
GH
20K
PWMH
+
-
Dead time and
shoot-through
logic
A
GND
-P
GND
level
shifter
2.5 V
V(T
J
) = 0.6 V + 8 mV x T
J
OT + V(T
max.
) V(T
J
) Temp.
-
sense
+
-
OCH
T
J
1 μs
pulse
REF
IN
+1.2 V
90 A
HFET
CSH
V
INPOR
OCH
Vishay Siliconix
2.5 V
LDO
V
CC
-
+
GH_BLANK
control
SW
V(T
J
)
CAL
and
level
shift
LFET
PV
CC
LS
driver
GL
GL_BLANK
control
CSL
REF
IN
IMON
+
-
PHASE
GL
OCH
OT
V
CCPOR
V
INPOR
LGCTRL TMON
NC
GND
FAULT#
OR function
Fig. 4 - Functional Block Diagram
ORDERING INFORMATION
PART NUMBER
SiC645ADR-T1-GE3
SiC645ALR-T1-GE3
SiC645AER-T1-GE3
SiC645ER-T1-GE3
MARKING CODE
45D
45L
45E
45E
TEMPERATURE
RANGE (°C)
-40 to +85
-10 to +100
-40 to +125
-40 to +125
PWM INPUT
(V)
3.3
3.3
3.3
5
PACKAGE (RoHS-compliant)
Dual cooled PowerPAK MLP55-32L
Dual cooled PowerPAK MLP55-32L
Dual cooled PowerPAK MLP55-32L
Dual cooled PowerPAK MLP55-32L
S20-0486-Rev. C, 29-Jun-2020
Document Number: 65424
4
For technical questions, contact:
powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiC645, SiC645A
www.vishay.com
PINOUT CONFIGURATION
FAULT#
PHASE
TMON
32
Vishay Siliconix
BOOT
IMON
31
9
REF
IN
30
PWM
28
GND
29
V
IN
27
26
25
24
23
LGCTRL
1
V
CC
2
PV
CC
3
GND
4
GL
5
GND
6
GND
7
GND
8
10
11
12
13
14
15
16
V
IN
V
IN
V
IN
GND
33
V
IN
34
22
21
20
GND
GND
GND
GND
GND
35
19
18
17
Fig. 5 - Pinout Configuration
SW
SW
SW
SW
SW
SW
SW
SW
PIN CONFIGURATION
PIN NUMBER
1
2
3
4, 6, 7, 8, 17, 18,
19, 20, 29, 33, 35
5
9, 10, 11, 12,
13, 14, 15, 16
21, 22, 23, 27,
34
24
25
26
28
30
NAME
LGCTRL
V
CC
PV
CC
GND
NC
SW
V
IN
PHASE
BOOT
FAULT#
PWM
REF
IN
FUNCTION
Lower gate control signal input. LO = GL LO (LFET off). HI = normal operation (GL and GH strictly obey
PWM). This pin should be driven with a logic signal, or externally tied high if not required; it should not
be left floating
+5 V logic bias supply. Place a high quality low ESR ceramic capacitor (~1 μF/X7R) in close proximity
from this pin to GND
+5 V gate drive bias supply. Place a high quality low ESR ceramic capacitor (~1 μF/X7R) in close
proximity from this pin to GND
GND pins are internally connected. Pins 4 and 29 should be connected directly to the nearby GND
paddles on package bottom. Fig. 15 shows GND paddles should be connected to the system GND
plane with as many vias as possible to maximize thermal and electrical performance.
No connect (This is a low side gate driver output (GL), optional to monitor for system debugging)
Switching junction node between HFET source and LFET drain. Connect directly to output inductor
Input of power stage (to drain of HFET). Place at least 2 ceramic capacitors (10 μF or higher, X5R or
X7R) in close proximity across V
IN
and GND. Pin 27 should not be used for decoupling. For optimal
performance, place as many vias as possible in the bottom side V
IN
paddle
Return of boot capacitor. Internally connected to SW node so no external routing required for SW
connection
Floating bootstrap supply pin for the upper gate drive. Place a high quality low ESR ceramic capacitor
(0.1 μF/X7R to 0.22 μF/X7R)i n close proximity across BOOT and PHASE pins
Open drain output pin. Any fault (over-current, over-temperature, shorted HFET, or POR / UVLO) will
pull this pin to ground. This pin may be connected to the controller enable pin or used to signal a fault
at the system level
PWM input of gate driver, compatible with 3.3 V and 5 V tri-state PWM signal
Input for external reference voltage for I
MON
signal. This voltage should be between 0.8 V and 1.6 V.
Connect REF
IN
to the appropriate current sense input of the controller. Place a high quality low ESR
ceramic capacitor (~ 0.1 μF) in close proximity from this pin to GND
Current monitor output, referenced to REF
IN
. I
MON
will be pulled high (to REF
IN
+1.2 V) to indicate an
HFET shorted or over-current fault. Connect the I
MON
output to the appropriate current sense input of
the controller. No more than 56 pF capacitance can be directly connected across I
MON
and REF
IN
pins.
With a 100
series resistor, up to 470 pF may be used
Temperature monitor output. For multiphase, the T
MON
pins can be connected together as a common
bus; the highest voltage (representing the highest temperature) will be sent to the PWM controller. T
MON
will be pulled high (to 2.5 V) to indicate an over-temperature fault. No more than 250 pF total
capacitance can be directly connected across T
MON
and GND pins; with a series resistor, a higher
capacitance load is allowed, such as 1 k for 100 nF load
31
I
MON
32
T
MON
S20-0486-Rev. C, 29-Jun-2020
Document Number: 65424
5
For technical questions, contact:
powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
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