MC74HC4046A
Phase−Locked Loop
High−Performance Silicon−Gate CMOS
The MC74HC4046A is similar in function to the MC14046 Metal
gate CMOS device. The device inputs are compatible with standard
CMOS outputs; with pullup resistors, they are compatible with
LSTTL outputs.
The HC4046A phase−locked loop contains three phase
comparators, a voltage−controlled oscillator (VCO) and unity gain
op−amp DEM
OUT
. The comparators have two common signal inputs,
COMP
IN
, and SIG
IN
. Input SIG
IN
and COMP
IN
can be used directly
coupled to large voltage signals, or indirectly coupled (with a series
capacitor to small voltage signals). The self−bias circuit adjusts small
voltage signals in the linear region of the amplifier. Phase comparator
1 (an exclusive OR gate) provides a digital error signal PC1
OUT
and
maintains 90 degrees phase shift at the center frequency between
SIG
IN
and COMP
IN
signals (both at 50% duty cycle). Phase
comparator 2 (with leading−edge sensing logic) provides digital error
signals PC2
OUT
and PCP
OUT
and maintains a 0 degree phase shift
between SIG
IN
and COMP
IN
signals (duty cycle is immaterial). The
linear VCO produces an output signal VCO
OUT
whose frequency is
determined by the voltage of input VCO
IN
signal and the capacitor
and resistors connected to pins C1A, C1B, R1 and R2. The unity gain
op−amp output DEM
OUT
with an external resistor is used where the
VCO
IN
signal is needed but no loading can be tolerated. The inhibit
input, when high, disables the VCO and all op−amps to minimize
standby power consumption.
Applications include FM and FSK modulation and demodulation,
frequency synthesis and multiplication, frequency discrimination,
tone decoding, data synchronization and conditioning,
voltage−to−frequency conversion and motor speed control.
Features
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MARKING
DIAGRAMS
16
16
1
PDIP−16
N SUFFIX
CASE 648
1
16
16
1
SOIC−16
D SUFFIX
CASE 751B
1
16
16
1
TSSOP−16
DT SUFFIX
CASE 948F
1
16
16
1
SOEIAJ−16
F SUFFIX
CASE 966
1
74HC4046A
ALYWG
HC40
46A
ALYWG
G
HC4046AG
AWLYWW
MC74HC4046AN
AWLYYWWG
•
•
•
•
•
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
Low Power Consumption Characteristic of CMOS Devices
Operating Speeds Similar to LSTTL
Wide Operating Voltage Range: 3.0 to 6.0 V
Low Input Current: 1.0
mA
Maximum (except SIG
IN
and COMP
IN
)
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Low Quiescent Current: 80
mA
Maximum (VCO disabled)
High Noise Immunity Characteristic of CMOS Devices
Diode Protection on all Inputs
Chip Complexity: 279 FETs or 70 Equivalent Gates
Pb−Free Packages are Available*
A
= Assembly Location
L, WL
= Wafer Lot
Y, YY
= Year
W, WW = Work Week
G
= Pb−Free Package
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2005
1
June, 2005 − Rev. 8
Publication Order Number:
MC74HC4046A/D
MC74HC4046A
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Symbol
PCP
OUT
PC1
OUT
COMP
IN
VCO
OUT
INH
C1A
C1B
GND
VCO
IN
DEM
OUT
R1
R2
PC2
OUT
SIG
IN
PC3
OUT
V
CC
Name and Function
Phase Comparator Pulse Output
Phase Comparator 1 Output
Comparator Input
VCO Output
Inhibit Input
Capacitor C1 Connection A
Capacitor C1 Connection B
Ground (0 V) V
SS
VCO Input
Demodulator Output
Resistor R1 Connection
Resistor R2 Connection
Phase Comparator 2 Output
Signal Input
Phase Comparator 3 Output
Positive Supply Voltage
PCP
out
PC1
out
COMP
in
VCO
out
INH
C1A
C1B
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
PC3
out
SIG
in
PC2
out
R2
R1
DEM
out
VCO
in
Figure 1. Pin Assignment
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Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS
Symbol
V
CC
V
in
Parameter
Value
Unit
V
V
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
– 0.5 to + 7.0
– 1.5 to V
CC
+ 1.5
– 0.5 to V
CC
+ 0.5
±
20
±
25
±
50
750
500
V
out
I
in
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
mA
mA
mA
I
out
DC Output Current, per Pin
I
CC
P
D
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air
Storage Temperature
Plastic DIP†
SOIC Package†
mW
_C
_C
T
stg
T
L
– 65 to + 150
260
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP and SOIC Package†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND
v
(V
in
or V
out
)
v
V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
Maximum ratings are those values beyond which device damage can occur. Maximum ratings
applied to the device are individual stress limit values (not normal operating conditions) and are not
valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Î Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î
Î
Î
ÎÎÎ Î Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎ Î Î
Î Î
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Î
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î
Î Î Î
Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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Î Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î
Î
ÎÎÎÎÎ Î
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Î Î Î
Î
Î
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Symbol
V
CC
Parameter
Min
3.0
Max
6.0
Unit
V
DC Supply Voltage (Referenced to GND)
V
CC
DC Supply Voltage (Referenced to GND) NON−VCO
2.0
0
6.0
V
V
in
, V
out
T
A
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time
(Pin 5)
V
CC
V
– 55
0
0
0
+ 125
1000
500
400
_C
ns
t
r
, t
f
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
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2
MC74HC4046A
[Phase Comparator Section]
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Guaranteed Limit
Symbol
V
IH
Parameter
Minimum High−Level Input
Voltage DC Coupled
SIG
IN
, COMP
IN
Maximum Low−Level Input
Voltage DC Coupled
SIG
IN
, COMP
IN
Minimum High−Level
Output Voltage
PCP
OUT
, PCn
OUT
Test Conditions
V
out
= 0.1 V or V
CC
− 0.1 V
|I
out
|
≤
20
mA
V
out
= 0.1 V or V
CC
− 0.1 V
|I
out
|
≤
20
mA
V
in
= V
IH
or V
IL
|I
out
|
≤
20
mA
V
in
= V
IH
or V
IL
|I
out
|
≤
4.0 mA
|I
out
|
≤
5.2 mA
V
OL
Maximum Low−Level
Output Voltage Qa−Qh
PCP
OUT
, PCn
OUT
V
out
= 0.1 V or V
CC
− 0.1 V
|I
out
|
≤
20
mA
V
in
= V
IH
or V
IL
|I
out
|
≤
4.0 mA
|I
out
|
≤
5.2 mA
I
in
Maximum Input Leakage Current
SIG
IN
, COMP
IN
V
in
= V
CC
or GND
V
CC
V
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
3.0
4.5
6.0
6.0
– 55 to
25_C
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
±
3.0
±
7.0
±
18.0
±
30.0
±
0.5
≤
85°C
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±
4.0
±
9.0
±
23.0
±
38.0
±
5.0
≤
125°C
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±
5.0
±
11.0
±
27.0
±
45.0
±
10
mA
V
Unit
V
V
IL
V
V
OH
V
I
OZ
Maximum Three−State
Leakage Current
PC2
OUT
Maximum Quiescent Supply Current
(per Package) (VCO disabled)
Pins 3, 5 and 14 at V
CC
Pin 9 at GND; Input Leakage at
Pins 3 and 14 to be excluded
Output in High−Impedance State
V
in
= V
IH
or V
IL
V
out
= V
CC
or GND
V
in
= V
CC
or GND
|I
out
| = 0
mA
mA
I
CC
6.0
4.0
40
160
mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book
(DL129/D).
[Phase Comparator Section]
AC ELECTRICAL CHARACTERISTICS
(C
L
= 50 pF, Input t
r
= t
f
= 6.0 ns)
Guaranteed Limit
Symbol
t
PLH
,
t
PHL
t
PLH
,
t
PHL
t
PLH
,
t
PHL
t
PLZ
,
t
PHZ
t
PZH
,
t
PZL
t
TLH
,
t
THL
Parameter
Maximum Propagation Delay, SIG
IN
/COMP
IN
to PC1
OUT
(Figure 2)
Maximum Propagation Delay, SIG
IN
/COMP
IN
to PCP
OUT
(Figure 2)
Maximum Propagation Delay, SIG
IN
/COMP
IN
to PC3
OUT
(Figure 2)
Maximum Propagation Delay, SIG
IN
/COMP
IN
Output
Disable Time to PC2
OUT
(Figures 3 and 4)
Maximum Propagation Delay, SIG
IN
/COMP
IN
Output
Enable Time to PC2
OUT
(Figures 3 and 4)
Maximum Output Transition Time
(Figure 2)
V
CC
V
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
– 55 to
25_C
175
35
30
340
68
58
270
54
46
200
40
34
230
46
39
75
15
13
≤
85°C
220
44
37
425
85
72
340
68
58
250
50
43
290
58
49
95
19
16
≤
125°C
265
53
45
510
102
87
405
81
69
300
60
51
345
69
59
110
22
19
Unit
ns
ns
ns
ns
ns
ns
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3
MC74HC4046A
[VCO Section]
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Guaranteed Limit
Symbol
V
IH
Parameter
Minimum High−Level
Input Voltage
INH
Maximum Low−Level
Input Voltage
INH
Minimum High−Level
Output Voltage
VCO
OUT
Test Conditions
V
out
= 0.1 V or V
CC
− 0.1 V
|I
out
|
≤
20
mA
V
out
= 0.1 V or V
CC
− 0.1 V
|I
out
|
≤
20
mA
V
in
= V
IH
or V
IL
|I
out
|
≤
20
mA
V
in
= V
IH
or V
IL
|I
out
|
≤
4.0 mA
|I
out
|
≤
5.2 mA
V
OL
Maximum Low−Level
Output Voltage
VCO
OUT
V
out
= 0.1 V or V
CC
− 0.1 V
|I
out
|
≤
20
mA
V
in
= V
IH
or V
IL
|I
out
|
≤
4.0 mA
|I
out
|
≤
5.2 mA
I
in
Maximum Input Leakage
Current INH, VCO
IN
V
in
= V
CC
or GND
V
CC
V
3.0
4.5
6.0
3.0
4.5
6.0
3.0
4.5
6.0
4.5
6.0
3.0
4.5
6.0
4.5
6.0
6.0
Min
V
VCO
IN Operating Voltage Range at
VCO
IN
over the range
specified for R1; For linearity
see Fig. 15A, Parallel value of
R1 and R2 should be > 2.7 kW
R1
Resistor Range
INH = V
IL
3.0
4.5
6.0
0.1
0.1
0.1
– 55 to
25_C
2.1
3.15
4.2
0.90
1.35
1.8
1.9
4.4
5.9
3.98
5.48
0.1
0.1
0.1
0.26
0.26
0.1
Max
1.0
2.5
4.0
Min
0.1
0.1
0.1
≤
85°C
2.1
3.15
4.2
0.9
1.35
1.8
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
1.0
Max
1.0
2.5
4.0
Min
0.1
0.1
0.1
≤
125°C
2.1
3.15
4.2
0.9
1.35
1.8
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
1.0
Max
1.0
2.5
4.0
V
mA
V
Unit
V
V
IL
V
V
OH
V
3.0
4.5
6.0
3.0
4.5
6.0
3.0
3.0
3.0
3.0
3.0
3.0
40
40
40
300
300
300
300
300
300
No
Limit
3.0
3.0
3.0
3.0
3.0
3.0
300
300
300
300
300
300
3.0
3.0
3.0
3.0
3.0
3.0
300
300
300
300
300
300
kW
R2
C1
Capacitor Range
3.0
4.5
6.0
pF
[VCO Section]
AC ELECTRICAL CHARACTERISTICS
(C
L
= 50 pF, Input t
r
= t
f
= 6.0 ns)
Guaranteed Limit
V
CC
V
3.0
4.5
6.0
3.0
4.5
6.0
3.0
4.5
6.0
3.0
4.5
6.0
3
11
13
See Figures 16A, B, C
– 55 to
25_C
Min
Max
≤
85°C
Min
Max
≤
125°C
Min
Max
Unit
%/K
Symbol
Df/T
Frequency Stability with
Temperature Changes
(Figure 14A, B, C)
VCO Center Frequency
(Duty Factor = 50%)
(Figure 15A, B, C, D)
VCO Frequency Linearity
Parameter
fo
MHz
DfVCO
%
∂
VCO
Duty Factor at VCO
OUT
Typical 50%
%
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4
MC74HC4046A
[Demodulator Section]
DC ELECTRICAL CHARACTERISTICS
Guaranteed Limit
– 55 to
25_C
Min
50
50
50
Max
300
300
300
See Figure 13
≤
85°C
Min
Max
≤
125°C
Min
Max
Unit
kW
Symbol
RS
Parameter
Resistor Range
Test Conditions
At RS > 300 kW the
Leakage Current can
Influence VDEM
OUT
Vi = VVCO
IN
= 1/2 V
CC
;
Values taken over RS
Range.
VDEM
OUT
= 1/2 V
CC
V
CC
V
3.0
4.5
6.0
3.0
4.5
6.0
3.0
4.5
6.0
V
OFF
Offset Voltage
VCO
IN
to VDEM
OUT
Dynamic Output
Resistance at DEM
OUT
mV
RD
Typical 25
W
W
ORDERING INFORMATION
Device
MC74HC4046AN
MC74HC4046ANG
MC74HC4046AD
MC74HC4046ADG
MC74HC4046ADR2
MC74HC4046ADR2G
MC74HC4046ADT
MC74HC4046ADTG
MC74HC4046ADTR2
MC74HC4046ADTR2G
MC74HC4046AF
MC74HC4046AFG
MC74HC4046AFEL
MC74HC4046AFELG
Package
PDIP−16
PDIP−16
(Pb−Free)
SOIC−16
SOIC−16
(Pb−Free)
SOIC−16
SOIC−16
(Pb−Free)
TSSOP−16*
TSSOP−16*
TSSOP−16*
TSSOP−16*
SOEIAJ−16
SOEIAJ−16
(Pb−Free)
SOEIAJ−16
SOEIAJ−16
(Pb−Free)
Shipping
†
2000 Units / Box
2000 Units / Box
48 Units / Rail
48 Units / Rail
2500 Units / Reel
2500 Units / Reel
96 Units / Rail
96 Units / Rail
2500 Units / Reel
2500 Units / Reel
50 Units / Rail
50 Units / Rail
2000 Units / Reel
2000 Units / Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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5
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