PAQ65D48 Series
High Efficiency Dual Output Quarter Brick DC-DC Converters
Features
u
Industry Standard Package
u
Low voltage outputs to 1.8V
u
Output Currents up to 17A
u
Designed for telecom standards
u
Output voltage adjustment - independent or tracking (/C)
u
Remote On / Off
u
High Efficiency
u
ASIC Design
u
No minimum load
Key Market Segments & Applications
Specifications
Model
Nominal Output Voltage
Output Current (Max)
Output Current (Max total)
Max Output Power
Efficiency (Typ)
Input Voltage range
Input Current (typ)
Output Voltage Accuracy
Output Voltage Trim Range (1)
Max Ripple & Noise
Max Line Regulation
Max Load Regulation
Overcurrent Protection (OCP) (2)
Overvoltage Protection (OVP)
Remote On / Off
Operating Temperature
Operating & Storage Humidity
Storage Temperature
Cooling
I/O Isolation Voltage
Vibration (non operating)
Shock
Safety Agency Approvals
Weight (Typ)
Size (WxHxD)
Warranty
VDC
A
A
W
%
VDC
A
%
VDC
mV
mV
mV
%
%
%
°C
-
°C
-
-
-
m/s
2
-
g
mm
yr
PAQ65D482518
V01
V02
2.5
15
37.5
86.0
0.82
1.8
17
PAQ65D483318
V01
V02
3.3
15
49.5
86.0
36 - 76V
0.97
1.10
1.36
±2
2.25-2.75 1.62-1.98 2.97-3.63 1.62-1.98 2.97-3.63 2.25-2.75 4.50-5.50 2.97-3.63
75
75
100
75
100
75
100
100
± 6.6
± 10
± 6.6
± 16.5
± 25
± 16.5
105 - 160% (See options table for either manual or automatic reset)
120 - 140% (See options table for either manual or automatic reset)
Low = ON, Open = OFF /P option; Low = OFF, Open = ON (See options)
-40°C to +85°C
5 - 95% RH, Non condensing
-40°C to +100°C
Convection, or forced air
Input to Output 1.5k VDC for 1 min.
10 - 55Hz (1 minute), amplitude 0.825mm (49m/s
2
max), X, Y, Z 1 hour each
196.1 m/s
2
UL1950, CSA950, EN60950, & CE
40
36.8 x 8.9 x 57.9 (36.8 x 10.2 x 57.9 /C version)
2 Years
PAQ65D483325
V01
V02
2.5
17
49.5
87.0
PAQ65D485033
V01
V02
5.0
13
65.0
90.0
3.3
16
1.8
3.3
17
15
Io1 + Io2 = 18
Note: See Installation Manual for full details, test methods of parameters and application notes.
1. Specify /C option for one trim pin - tracking outputs, leave blank for individual adjustment
2. lo1 + lo2
Not recommended for new designs
1-800-526-2324 • www.us.tdk-lambda.com/lp/
13
PAQ65D48 Series
Outline Drawing (/C versions)
Outline Drawing (non /C versions)
Connection Example
Measurement point for Vin
Measurement point for Vo,
line & load regulation
Measurement point for output ripple & noise
Bandwidth for scope : 20MHz
MADE IN MALAYSIA
DENSEI-LAMBDA
MADE IN MALAYSIA
DENSEI-LAMBDA
Options
Suffix
Trim Pin
On/Off Logic
Blank
Independent
Negative, short = ON
/P
-
Positive, Open = ON
/V
-
-
/C
Tracking
-
/V, /PV, /CV, /CPV are US Standard US stock items
Note suffix letter order : /C followed by P followed by V
OVP /OCP
Manual Reset
-
Auto-restart
-
Fuse 5A *1
+Vin
Vo1
C2 22uF *3
Trim 1
Gnd
CNT
Trim 2
C3 22uF *3
Vo2
-Vin
C1 *2
+
-
Load
Vin
36~76 VDC
+
-
+
Load
L=50mm
Other DC-DC Products
X
PAF
PAH
PAQ
SX
10, 15, & 20W 24V & 48VDC input DC-DC converters
500 & 600W Full brick DC-DC
50W to 200W Half brick DC-DC, single & dual outputs
Up to 100W Quarter brick DC-DC, single outputs
20W surface mount 24V & 48VDC-DC
For Additional Information, please visit
us.tdk-lambda.com/lp/products/paq-series.htm
Not recommended for new designs
1-800-526-2324 • www.us.tdk-lambda.com/lp/
14
Revision A2: Feb 2012
FPGA/CPLD
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