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Reference:CMV300-datasheet-v2.10
CMV300 Datasheet
Page 1 of 55
VGA resolution CMOS image sensor
Datasheet
© 2016 CMOSIS bvba
Reference:CMV300-datasheet-v2.10
CMV300 Datasheet
Change record
Issue
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
2.0
Date
13/04/2011
5/8/2011
20/10/2011
25/4/2012
22/08/2012
28/09/2012
19/12/2012
8/1/2012
05/06/2013
Modification
Origination
Update after tape out
Update after samples test and debug
Updated maximum output rate from 600Mbps to 300 Mbps
Updated recommended register values
Added Spectral Response and QE graphs
Updated recommended register values
Updated supply settings
Removed Draft status
Updated Part Numbers
Updated VDD18 range
Updated:
- maximum output rate from 300Mbps to 480Mbps
- Full Well Charge: 20ke
-
- Conversion factor: 0.2LSB/e
-
- Dynamic range: 60dB
- Dark current: 125e
-
/s
- Total power: 700mW
- VDDPIX: 3.3V
- VDD18 renamed to VDD20
- Supply settings
- FOT calculation and value
- Piecewise Linear Response details
- PLR external mode pulse requirements
- Bit mode details
- Recommended registers
Added:
- Temperature sensor formulas and graphs
- Output skew
- Control channel test pin (Test3) programming
- Disable PLL
- Actual exposure calculations
- ADC vs actual gain
- Detailed frame cycle timing
Updated:
- Detailed frame cycle timing
- Exposure calculation
Added:
- Color and mono QE
Updated:
- VDDPIX to 3.0V
- Recommended value for reg 106 = 90
Updated:
- Exposure time calculation
Page 2 of 55
V2.1
03/07/2013
V2.2
08/07/2013
V2.3
20/08/2013
© 2016 CMOSIS bvba
Reference:CMV300-datasheet-v2.10
CMV300 Datasheet
Issue
V2.4
Date
05/03/2014
Modification
Updated:
- Assembly thickness dimensions (details PCN-01)
- Added ‘0’-bits in 8/10bit are LSB
- Ch5.7: reg69 to 9 for parallel output mode
- Piecewise Linear response Figure 32
- PLL settings ch. 5.10
- Disable PLL settings ch. 5.11
- LVDS output skew
- Part Number
Added:
- Location of pixel(0,0) in assembly drawing
- Limitations when using or disabling the PLL (ch. 5.10
& ch.5.11)
Updated:
- FOT description (ch 3.6)
- Exposure timing (ch 5.1)
- SPI_OUT is low when SPI_EN is low
- No TP between FOT and FVAL (ch 4.1.5)
- Supply settings
- Rename VDD18 to VDD20 in pin list
- Reflow soldering details (ch 12.1.1)
Added:
- MSL-5 (ch 12.1)
Removed:
- Wave soldering
Updated:
- Baking condition 24h-48h
12h
- SPI I/O’s are pulled low when not enabled
- Frame rate calculation ch 3.6
- Fig. Figure 30: Frame cycle timing
- Assembly drawing
Added:
- Figure 27: Detailed timing diagram
- Excessive light precaution
Updated:
- Removed ES label from part numbers
- Temperature sensor typical values
- ADC vs. clock speed
Added:
- Test image
Updated:
- Reflow profile
Updated:
- MSL and solder profile following J-STD-020
- Replaced “1.8V” notations with VDD20
Added:
- ESD level
Updated:
- Recommended PLL reg83 187
155 (for 40MHz)
Added:
- Exposure delay
- Pin list connection to internal blocks
Disclaimer
© 2016 CMOSIS bvba
Page 3 of 55
V2.5
28/10/2014
V2.6
19/06/2015
V2.7
09/09/2015
V2.8
12/10/2015
V2.9
23/10/2015
V2.10
29/02/2016
Reference:CMV300-datasheet-v2.10
CMV300 Datasheet
Page 4 of 55
This is a preliminary datasheet. CMOSIS reserves the right to change the product, specification and other information
contained in this document without notice. Although CMOSIS does its best efforts to provide correct information, this
is not warranted.
© 2016 CMOSIS bvba