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SIT9121AC-1DF-33E75.497472T

产品描述OSC MEMS 75.497472MHZ LVPECL SMD
产品类别无源元件   
文件大小360KB,共8页
制造商SiTime
标准
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SIT9121AC-1DF-33E75.497472T概述

OSC MEMS 75.497472MHZ LVPECL SMD

SIT9121AC-1DF-33E75.497472T规格参数

参数名称属性值
类型MEMS(硅)
频率75.497472MHz
功能启用/禁用
输出LVPECL
电压 - 电源3.3V
频率稳定度±10ppm
工作温度-20°C ~ 70°C
电流 - 电源(最大值)69mA
安装类型表面贴装
封装/外壳6-SMD,无引线
大小/尺寸0.276" 长 x 0.197" 宽(7.00mm x 5.00mm)
高度 - 安装(最大值)0.039"(1.00mm)
电流 - 电源(禁用)(最大值)35mA

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SiT9121
1-220 MHz High Performance Differential Oscillator
The Smart Timing Choice
Features
Applications
Any frequency between 1 MHz and 220 MHz accurate to 6 decimal
places
LVPECL and LVDS output signaling types
0.6ps RMS phase jitter (random) over 12 kHz to 20 MHz bandwidth
Frequency stability as low as ±10 ppm
Industrial and extended commercial temperature ranges
Industry-standard packages: 3.2x2.5, 5.0x3.2 and 7.0x5.0 mmxmm
For frequencies higher than 220 MHz, refer to SiT9122 datasheet
10GB Ethernet, SONET, SATA, SAS, Fibre Channel,
PCI-Express
Telecom, networking, instrumentation, storage, servers
Electrical Characteristics
Parameter and Conditions
Supply Voltage
Symbol
Vdd
Min.
Typ.
Max.
Unit
Condition
LVPECL and LVDS, Common Electrical Characteristics
2.97
2.25
2.25
Output Frequency Range
Frequency Stability
f
F_stab
1
-10
-20
-25
-50
First Year Aging
10-year Aging
Operating Temperature Range
Input Voltage High
Input Voltage Low
Input Pull-up Impedance
F_aging1
F_aging10
T_use
VIH
VIL
Z_in
-2
-5
-40
-20
70%
2
Start-up Time
Resume Time
Duty Cycle
T_start
T_resume
DC
45
3.3
2.5
100
6
6
3.63
2.75
3.63
220
+10
+20
+25
+50
+2
+5
+85
+70
30%
250
10
10
55
V
V
V
MHz
ppm
ppm
ppm
ppm
ppm
ppm
°C
°C
Vdd
Vdd
ms
ms
%
25°C
25°C
Industrial
Extended Commercial
Pin 1, OE or
ST
Pin 1, OE or
ST
Pin 1, OE logic high or logic low, or
ST
logic high
Pin 1,
ST
logic low
Measured from the time Vdd reaches its rated minimum value.
In Standby mode, measured from the time
ST
pin
crosses 50% threshold.
Contact SiTime for tighter duty cycle
Inclusive of initial tolerance, operating temperature, rated power
supply voltage, and load variations
Termination schemes in Figures 1 and 2 - XX ordering code
LVPECL, DC and AC Characteristics
Current Consumption
OE Disable Supply Current
Output Disable Leakage Current
Standby Current
Maximum Output Current
Output High Voltage
Output Low Voltage
Output Differential Voltage Swing
Rise/Fall Time
OE Enable/Disable Time
RMS Period Jitter
Idd
I_OE
I_leak
I_std
I_driver
VOH
VOL
V_Swing
Tr, Tf
T_oe
T_jitt
Vdd-1.1
Vdd-1.9
1.2
61
1.6
300
1.2
1.2
1.2
0.6
69
35
1
100
30
Vdd-0.7
Vdd-1.5
2.0
700
115
1.7
1.7
1.7
0.85
mA
mA
µA
µA
mA
V
V
V
ps
ns
ps
ps
ps
ps
Excluding Load Termination Current, Vdd = 3.3V or 2.5V
OE = Low
OE = Low
ST
= Low, for all Vdds
Maximum average current drawn from OUT+ or OUT-
See Figure 1(a)
See Figure 1(a)
See Figure 1(b)
20% to 80%, see Figure 1(a)
f = 212.5 MHz - For other frequencies, T_oe = 100ns + 3 period
f = 100 MHz, VDD = 3.3V or 2.5V
f = 156.25 MHz, VDD = 3.3V or 2.5V
f = 212.5 MHz, VDD = 3.3V or 2.5V
f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz, all
Vdds
Excluding Load Termination Current, Vdd = 3.3V or 2.5V
OE = Low
See Figure 2
RMS Phase Jitter (random)
T_phj
LVDS, DC and AC Characteristics
Current Consumption
OE Disable Supply Current
Differential Output Voltage
Idd
I_OE
VOD
250
47
350
55
35
450
mA
mA
mV
SiTime Corporation
Rev. 1.07
990 Almanor Avenue, Sunnyvale, CA 94085
(408) 328-4400
www.sitime.com
Revised January 4, 2016

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