MGA-17516
Low Noise, High Linearity Match Pair Low Noise Amplifier
Data Sheet
Description
Avago Technologies’ MGA-17516 is an economical,
easy-to-use GaAs MMIC match pair Low Noise Amplifier
(LNA). The LNA has low noise and high linearity achieved
through the use of Avago Technologies’ proprietary
0.25um GaAs Enhancement-mode pHEMT process. It is
housed in a miniature 4.0 x 4.0 x 0.85mm
3
16-pin Quad-
Flat-Non-Lead (QFN) package. The compact footprint and
low profile coupled with low noise, high gain and high
linearity make the MGA-17516 an ideal choice as a low
noise amplifier for cellular infrastructure for GSM, CDMA
and TDS-CDMA applications. This device is applicable to
both Single and Balance mode. It is designed for optimum
use from 1.7GHz to 2.7GHz. For optimum performance at
lower frequency from 500MHz to 1.7GHz, the MGA-16516
is recommended. Both MGA-17516 and MGA-16516 share
the same package and pinout.
Features
x
4.0 x 4.0 x 0.85 mm
3
16-lead QFN
x
Low noise figure
x
High linearity performance
x
GaAs E-pHEMT Technology
[1]
x
Low cost small package size: 4.0x4.0x0.85 mm
3
x
Excellent uniformity in product specifications
x
Tape-and-Reel packaging option available
Specifications
1.85GHz; 5V, 50mA (typ) per section
x
17.4 dB Gain
x
0.46 dB Noise Figure
x
16.2 dBm Input IP3
x
21 dBm Output Power at 1dB gain compression
Pin Configuration and Package Marking
Pin 13
Pin 14
Pin 16
Pin 16
Applications
x
Low noise amplifier for cellular infrastructure for GSM,
CDMA and TDS-CDMA.
Pin 1
Pin 2
Pin 3
Pin 4
17516
YYWW
XXXX
Pin 12
Pin 11
Pin 10
Pin 9
x
Other ultra low noise application.
GND
TOP VIEW
BOTTOM VIEW
Note:
Package marking provides orientation and identification
“17516” = Device Code
“YYWW“ = Year and Work Week
“XXXX” = Last 4 digit of Device Lot Number
Attention: Observe precautions for
handling electrostatic sensitive devices.
ESD Machine Model = 40 V
ESD Human Body Model = 350 V
Refer to Avago Application Note A004R:
Electrostatic Discharge, Damage and Control.
Pin 8
Pin 7
Pin 6
Pin 5
Pin Configuration
[4]
[3]
[2]
[1]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[16]
[15]
[14]
[13]
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Use
Not Used
Not Used
Not Used
Not Used
RFin1
Not Used
Not Used
RFin2
Not Used
Not Used
Not Used
Not Used
RFout2
Not Used
Not Used
RFout1
Simplified Schematic
Vgg1
Ca7
Ca5
Vdd1
Ca11
Ca9
Ra1
L1
[4]
[3]
[2]
[1]
Ra4
L2
[16]
[15]
[14]
[13]
RFin a
RFin b
C1
C3
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
C2
C4
RFout a
RFout b
L3
Cb5
Cb7
Rb1
Vgg2
L4
Rb4 Cb9
Vdd2
Cb11
Note:
x
Enhancement mode technology employs positive gate voltage,
thereby eliminating the need of negative gate voltage associated
with conventional depletion mode devices.
2
Absolute Maximum Rating
[2]
T
A
= 25°C
Symbol
V
dd
V
gg
P
in
I
dd
P
diss
T
j
T
STG
Parameter
Device Voltage, RF output to ground
Gate Voltage
CW RF Input Power
(V
dd
= 5.0, I
dd
= 50mA)
Device Current,
RFout to ground per channel
Total Power Dissipation
[4]
Junction Temperature
Storage Temperature
Units
V
V
dBm
mA
W
°C
°C
Absolute Max.
5.5
1
15
100
1
150
-65 to 150
Thermal Resistance
[3]
(V
dd
= 5.0V, I
dd
= 50mA per channel),
T
jc
= 49.4°C/W per channel
Notes:
2. Operation of this device in excess of any of
these limits may cause permanent damage.
3. Thermal resistance measured using Infra-Red
Measurement Technique with both channels
turned on hence I
dd_total
=100mA.
4. Power dissipation with both channels turned
on. Board temperature T
B
is 25°C. Derate at
20mW/°C for T
B
>100°C.
Electrical Specifications
[7-10]
RF performance at T
A
= 25°C, V
dd
=5V, I
dd
= 50mA, 1.85 GHz and 1.95 GHz given for each RF channel, measured on demo
board in Figure 5 with component list in Table1 for 1.85GHz matching.
Symbol
V
gg
Gain
IIP3
[8]
NF
[9]
OP1dB
IRL
ORL
REV ISOL
ISOL
1-2
Parameter and Test Condition
Operational Gate Voltage, Idd=50mA
Gain
Input Third Order Intercept Point
Noise Figure
Output Power at 1dB Gain Compression
Input Return Loss, 50Ω source
Output Return Loss, 50Ω load
Reverse Isolation
Isolation between RFin1 and RFin2
Frequency (GHz)
1.85
1.95
1.85
1.95
1.85
1.95
1.85
1.95
1.85
1.95
1.85
1.95
1.85
1.95
1.85
1.95
Units
V
dB
dB
dBm
dBm
dB
dB
dBm
dBm
dB
dB
dB
dB
dB
dB
dB
dB
Min.
0.40
15.5
13.5
Typ.
0.53
17.4
16.8
16.2
17
0.46
0.50
21
21
6
6.3
15
15
26
26
38
38
Max.
0.65
18.5
0.75
Notes:
7. Measurements at 1.85 GHz obtained using demo board described in Figure 1.
8. IIP3 test condition:
a. F
RF1
= 1.85 GHz, F
RF2
= 1.851 GHz with input power of -15dBm per tone.
b. F
RF1
= 1.95 GHz, F
RF2
= 1.951GHz with input power of -15dBm per tone.
9. For NF data, board losses of the input have not been de-embedded.
10. Use proper bias, heatsink and derating to ensure maximum channel temperature is not exceeded. See absolute maximum ratings and application
note for more details.
3
Product Consistency Distribution Charts
Mean : 0.53
Min : 0.40
Max : 0.65
Mean : 0.50
Max : 0.75
Figure 1. Vgg @ 1.95GHz, 5V, 50mA
Mean = 0.53
Figure 2. Noise Figure @ 1.95GHz, 5V, 50mA
Mean = 0.50
Mean : 17.0
Min : 13.5
Mean : 16.8
Min : 15.5
Max : 18.5
Figure 3. IIP3 @ 1.95GHz, 5V, 50mA
Mean = 17.0
Figure 4. Gain @ 1.95GHz, 5V, 50mA
Mean = 16.8
Notes:
1. Distribution data samples size is 500 samples taken from 4 different wafers. Future wafers allocated to this product may have nominal values
anywhere between the upper and lower limits. Circuit losses have not been de-embedded from actual measurement.
4
Demo Board Layout
– Recommended PCB material is 10 mils Rogers RO4350.
– Suggested component values may vary according to
layout and PCB material.
Figure 5. Demo Board Layout Diagram
Demo Board Schematic
Vgg1
Vdd1
Table 1. Component list for 1.85GHz matching.
Part
Size
0402
0402
0805
0805
0402
0402
0402
0402
0402
0402
Value
1000pF (Murata)
1000pF (Murata)
4.7uF (Murata)
4.7uF (Murata)
9pF (Murata)
9pF (Murata)
4.3: (Rohm)
9.1: (Rohm)
9nH (Coilcraft)
8.2nH (Toko)
Part Number
GRM155R71H102KA01
GRM155R71H102KA01
GRM21BR60J475KA11L
GRM21BR60J475KA11L
GJM1555C1H9R0CB01
GJM1555C1H9R0CB01
MCR01MZSJ4R3
MCRO1MZSJ9R1
0402CS-9N0XJLU
LLP1005-FH8N2C
Ca7
Ca5
Ca11
Ra1
Ra4
Ca9
L2
C2
[16]
[15]
[14]
[13]
[9]
[10]
[11]
[12]
C1, C2
C3, C4
Ca7, Ca11
Cb7, Cb11
Ca5, Ca9
L1
[4]
[3]
[2]
[1]
RFin a
C1
[5]
[6]
[7]
[8]
RFout a
Cb5, Cb9
Ra1, Rb1
RFin b
C3
C4
RFout b
Ra4, Rb4
L1, L3
L2, L4
L3
L4
Cb5
Cb7
Rb1
Rb4
Cb9
Cb11
Vgg2
Vdd2
Figure 6. Demo Board Schematic Diagram
5
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