NVT2003/04/06
Bidirectional voltage-level translator for open-drain and
push-pull applications
Rev. 5 — 19 February 2014
Product data sheet
1. General description
The NVT2003/04/06 is a family of bidirectional voltage level translators operational from
1.0 V to 3.6 V (V
ref(A)
) and 1.8 V to 5.5 V (V
ref(B)
), which allow bidirectional voltage
translations between 1.0 V and 5 V without the need for a direction pin in open-drain or
push-pull applications. Bit widths ranging from 3-bit to 6-bit are offered for level translation
application with transmission speeds < 33 MHz for an open-drain system with a 50 pF
capacitance and a pull-up of 197
.
When the An or Bn port is LOW, the clamp is in the ON-state and a low resistance
connection exists between the An and Bn ports. The low ON-state resistance (R
on
) of the
switch allows connections to be made with minimal propagation delay. Assuming the
higher voltage is on the Bn port when the Bn port is HIGH, the voltage on the An port is
limited to the voltage set by VREFA. When the An port is HIGH, the Bn port is pulled to the
drain pull-up supply voltage (V
pu(D)
) by the pull-up resistors. This functionality allows a
seamless translation between higher and lower voltages selected by the user without the
need for directional control.
When EN is HIGH, the translator switch is on, and the An I/O are connected to the Bn I/O,
respectively, allowing bidirectional data flow between ports. When EN is LOW, the
translator switch is off, and a high-impedance state exists between ports. The EN input
circuit is designed to be supplied by V
ref(B)
. To ensure the high-impedance state during
power-up or power-down, EN must be LOW.
All channels have the same electrical characteristics and there is minimal deviation from
one output to another in voltage or propagation delay. This is a benefit over discrete
transistor voltage translation solutions, since the fabrication of the switch is symmetrical.
The translator provides excellent ESD protection to lower voltage devices, and at the
same time protects less ESD-resistant devices.
2. Features and benefits
Provides bidirectional voltage translation with no direction pin
Less than 1.5 ns maximum propagation delay
Allows voltage level translation between:
1.0 V V
ref(A)
and 1.8 V, 2.5 V, 3.3 V or 5 V V
ref(B)
1.2 V V
ref(A)
and 1.8 V, 2.5 V, 3.3 V or 5 V V
ref(B)
1.8 V V
ref(A)
and 3.3 V or 5 V V
ref(B)
2.5 V V
ref(A)
and 5 V V
ref(B)
3.3 V V
ref(A)
and 5 V V
ref(B)
NXP Semiconductors
NVT2003/04/06
Bidirectional voltage-level translator
Low 3.5
ON-state connection between input and output ports provides less signal
distortion
5 V tolerant I/O ports to support mixed-mode signal operation
High-impedance An and Bn pins for EN = LOW
Lock-up free operation
Flow through pinout for ease of printed-circuit board trace routing
ESD protection exceeds 3.5 kV HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
Packages offered: TSSOP10, HXSON12, DHVQFN16, HVQFN16, TSSOP16
3. Ordering information
Table 1.
Ordering information
Topside
marking
N2003
N4
Number Package
of bits
Name
3
4
TSSOP10
HXSON12
Description
plastic thin shrink small outline package; 10 leads;
body width 3 mm
Version
SOT552-1
Type number
NVT2003DP
NVT2004TL
plastic, thermal enhanced extremely thin small outline SOT973-2
package; no leads; 12 terminals;
body 1.35
2.5
0.5 mm
SOT763-1
NVT2006BQ
N2006
6
DHVQFN16 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads;16 terminals;
body 2.5
3.5
0.85 mm
HVQFN16
TSSOP16
plastic thermal enhanced very thin quad flat package;
no leads; 16 terminals; body 3
3
0.85 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
NVT2006BS
NVT2006PW
N06
NVT2006
6
6
SOT758-1
SOT403-1
3.1 Ordering options
Table 2.
Ordering options
Orderable
part number
NVT2003DP,118
NVT2004TL,115
NVT2006BQ,115
NVT2006BS,118
NVT2006PW,118
Package
TSSOP10
HXSON12
DHVQFN16
HVQFN16
TSSOP16
Packing method
Reel 13” Q1/T1
*Standard mark SMD
Reel 7” Q1/T1
*Standard mark SMD
Reel 7” Q1/T1
*Standard mark SMD
Reel 13” Q1/T1
*Standard mark SMD
Reel 13” Q1/T1
*Standard mark SMD
Minimum
order quantity
2500
4000
3000
6000
2500
Temperature
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
T
amb
=
40 C
to +85
C
Type number
NVT2003DP
NVT2004TL
NVT2006BQ
NVT2006BS
NVT2006PW
NVT2003_04_06
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 5 — 19 February 2014
2 of 33
NXP Semiconductors
NVT2003/04/06
Bidirectional voltage-level translator
4. Functional diagram
VREFA
VREFB
NVT20xx
EN
A1
SW
B1
An
SW
Bn
GND
002aae132
Fig 1.
Logic diagram of NVT2003/04/06 (positive logic)
5. Pinning information
5.1 Pinning
5.1.1 3-bit in TSSOP10 package
GND
VREFA
A1
A2
A3
1
2
3
4
5
002aae836
10 EN
9
VREFB
B1
B2
B3
8
7
6
NVT2003DP
Fig 2.
Pin configuration for TSSOP10
5.1.2 4-bit in HXSON12 package
NVT2004TL
GND
VREFA
A1
A2
A3
A4
1
2
3
4
5
6
12 EN
11 VREFB
10 B1
9
8
7
B2
B3
B4
002aae219
Transparent top view
Fig 3.
NVT2003_04_06
Pin configuration for HXSON12U
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 5 — 19 February 2014
3 of 33
NXP Semiconductors
NVT2003/04/06
Bidirectional voltage-level translator
5.1.3 6-bit in TSSOP16, DHVQFN16 and HVQFN16 packages
GND
2
3
4
5
6
7
8
A6
B6
9
1
terminal 1
index area
VREFA
A1
A2
A3
A4
A5
16 EN
15 VREFB
14 B1
13 B2
12 B3
11 B4
10 B5
GND
VREFA
A1
A2
A3
A4
A5
A6
1
2
3
4
5
6
7
8
002aae220
16 EN
15 VREFB
14 B1
13 B2
12 B3
11 B4
10 B5
9
B6
NVT2006BQ
NVT2006PW
002aae221
Transparent top view
Fig 4.
Pin configuration for TSSOP16
16 VREFA
Fig 5.
13 VREFB
Pin configuration for DHVQFN16
15 GND
terminal 1
index area
A1
A2
A3
A4
1
2
14 EN
12 B1
11 B2
NVT2006BS
3
4
5
6
7
8
10 B3
9
B4
A5
A6
B6
B5
002aae222
Transparent top view
Fig 6.
Pin configuration for HVQFN16
NVT2003_04_06
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 5 — 19 February 2014
4 of 33
NXP Semiconductors
NVT2003/04/06
Bidirectional voltage-level translator
5.2 Pin description
Table 3.
Symbol
Pin description
Pin
NVT2003DP
[1]
GND
VREFA
A1
A2
A3
A4
A5
A6
B1
B2
B3
B4
B5
B6
VREFB
EN
1
2
3
4
5
-
-
-
8
7
6
-
-
-
9
10
NVT2004TL
[2]
1
2
3
4
5
6
-
-
10
9
8
7
-
-
11
12
NVT2006BQ,
NVT2006PW
[3]
1
2
3
4
5
6
7
8
14
13
12
11
10
9
15
16
NVT2006BS
[3]
15
16
1
2
3
4
5
6
12
11
10
9
8
7
13
14
high-voltage side reference
supply voltage for Bn
switch enable input; connect to VREFB
and pull-up through a high resistor
high-voltage side; connect to VREFB
through a pull-up resistor
ground (0 V)
low-voltage side reference
supply voltage for An
low-voltage side; connect to VREFA
through a pull-up resistor
Description
[1]
[2]
[3]
3-bit NVT2003 available in TSSOP10 package.
4-bit NVT2004 available in HXSON12 package.
6-bit NVT2006 available in TSSOP16, DHVQFN16, HVQFN16 packages.
6. Functional description
Refer to
Figure 1 “Logic diagram of NVT2003/04/06 (positive logic)”.
6.1 Function table
Table 4.
Function selection (example)
H = HIGH level; L = LOW level.
Input EN
[1]
H
L
[1]
Function
An = Bn
disconnect
EN is controlled by the V
ref(B)
logic levels and should be at least 1 V higher than V
ref(A)
for best translator
operation.
NVT2003_04_06
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 5 — 19 February 2014
5 of 33
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