MC74HCT08A
Quad 2-Input AND Gate
with LSTTL Compatible
Inputs
High−Performance Silicon−Gate CMOS
The MC74HCT08A is identical in pinout to the LS08. The device
inputs are compatible with Standard CMOS or LSTTL outputs.
Features
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MARKING
DIAGRAMS
14
14
1
SOIC−14
D SUFFIX
CASE 751A
1
14
14
1
TSSOP−14
DT SUFFIX
CASE 948G
1
A
= Assembly Location
WL, L = Wafer Lot
YY, Y
= Year
WW, W = Work Week
G or
G
= Pb−Free Package
(Note: Microdot may be in either location)
Y = AB
8
Y3
A
11
Y4
L
L
H
H
HCT
08
ALYW
G
G
HCT08AG
AWLYWW
•
•
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2.0 V to 6.0 V
Low Input Current: 1
mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance With the JEDEC Standard No. 7A Requirements
Chip Complexity: 24 FETs or 6 Equivalent Gates
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
•
These are Pb−Free Devices
A1
B1
A2
B2
A3
B3
A4
B4
1
2
4
5
9
10
12
13
PIN 14 = V
CC
PIN 7 = GND
3
Y1
6
Y2
FUNCTION TABLE
Inputs
B
L
H
L
H
Output
Y
L
L
L
H
Figure 1. Logic Diagram
Pinout: 14−Lead Packages
(Top View)
V
CC
14
B4
13
A4
12
Y4
11
B3
10
A3
9
Y3
8
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
1
A1
2
B1
3
Y1
4
A2
5
B2
6
Y2
7
GND
Figure 2. Pinout
©
Semiconductor Components Industries, LLC, 2014
February, 2014
−
Rev. 9
1
Publication Order Number:
MC74HCT08A/D
MC74HCT08A
MAXIMUM RATINGS
Symbol
V
CC
V
in
V
out
I
in
I
out
I
CC
P
D
T
stg
T
L
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air,
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
SOIC or TSSOP Package
SOIC Package
†
TSSOP Package
†
Value
−0.5
to +7.0
−0.5
to V
CC
+0.5
−0.5
to V
CC
+0.5
±20
±25
±50
500
450
−65
to +150
260
Unit
V
V
V
mA
mA
mA
mW
°C
°C
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND
v
(V
in
or V
out
)
v
V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
†Derating
−
SOIC Package:
−
7 mW/°C from 65°C to 125°C
TSSOP Package:
−
6.1 mW/°C from 65°C to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
in
, V
out
T
A
t
r
, t
f
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage
(Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time
(Figure 3)
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Parameter
Min
2.0
0
−55
0
0
0
Max
6.0
V
CC
+125
1000
500
400
Unit
V
V
°C
ns
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2
MC74HCT08A
DC CHARACTERISTICS
(Voltages Referenced to GND)
Symbol
V
IH
V
IL
V
OH
Parameter
Minimum High−Level Input Voltage
Maximum Low−Level Input Voltage
Minimum High−Level Output Voltage
Condition
V
out
= 0.1 V or V
CC
−0.1
V
|I
out
|
≤
20
mA
V
out
= 0.1 V or V
CC
−
0.1 V
|I
out
|
≤
20
mA
V
in
= V
IH
or V
IL
|I
out
|
≤
20
mA
V
in
=V
IH
or V
IL
V
OL
Maximum Low−Level Output Voltage
V
in
= V
IH
or V
IL
|I
out
|
≤
20mA
V
in
= V
IH
or V
IL
I
in
I
CC
Maximum Input Leakage Current
Maximum Quiescent Supply
Current (per Package)
V
in
= V
CC
or GND
V
in
= V
CC
or GND
I
out
= 0
mA
|I
out
|
≤
4.0 mA
|I
out
|
≤
4.0 mA
V
CC
V
4.5 to
5.5
4.5 to
5.5
4.5
5.5
4.5
4.5
5.5
4.5
5.5
5.5
Guaranteed Limit
−55
to 25°C
2.0
0.8
4.4
5.4
3.98
0.1
0.1
0.26
±0.1
1.0
≤85°C
2.0
0.8
4.4
5.4
3.84
0.1
0.1
0.33
±1.0
10
≤125°C
2.0
0.8
4.4
5.4
3.70
0.1
0.1
0.40
±1.0
40
mA
mA
V
Unit
V
V
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
AC CHARACTERISTICS
(C
L
= 50 pF, Input t
r
= t
f
= 6 ns, V
CC
= 5.0 V
±
10%)
Symbol
t
PLH
,
t
PHL
t
TLH
,
t
THL
C
in
Parameter
Maximum Propagation Delay, Input A or B to Output Y
(Figures 3 and 4)
Maximum Output Transition Time, Any Output
(Figures 3 and 4)
Maximum Input Capacitance
t
PLH
t
PHL
V
CC
V
5.0
5.0
Guaranteed Limit
−55
to 25°C
15
17
15
10
≤85°C
19
21
19
10
≤125°C
22
26
22
10
Unit
ns
ns
pF
Typical @ 25°C, V
CC
= 5.0 V, V
EE
= 0 V
C
PD
Power Dissipation Capacitance (Per Buffer)*
2
f
20
+ I
CC
V
CC
.
pF
*Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC
ORDERING INFORMATION
Device
MC74HCT08ADG
MC74HCT08ADR2G
MC74HCT08ADTR2G
NLV74HCT08ADTR2G*
Package
SOIC−14
(Pb−Free)
TSSOP−14
(Pb−Free)
Shipping
†
55 Units / Rail
2500/Tape & Reel
2500/Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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3
MC74HCT08A
t
r
INPUT
A OR B
(V
I
)
V
I
= GND to 3.0 V
V
m
= 1.3 V
OUTPUT Y
t
PLH
90%
V
m
10%
t
TLH
t
THL
90%
V
m
10%
t
PHL
t
f
V
CC
GND
Figure 3. Switching Waveforms
TEST
POINT
OUTPUT
DEVICE
UNDER
TEST
C
L
*
*Includes all probe and jig capacitance
Figure 4. Test Circuit
A
B
Y
Figure 5. Expanded Logic Diagram
(1/4 of the Device)
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4
MC74HCT08A
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G
ISSUE B
M
14X
K
REF
0.10 (0.004)
0.15 (0.006) T U
S
T U
S
V
S
N
2X
L/2
14
8
0.25 (0.010)
M
L
PIN 1
IDENT.
1
7
B
−U−
N
F
DETAIL E
K
K1
J J1
0.15 (0.006) T U
S
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE
−W−.
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.50
0.60
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0
_
8
_
INCHES
MIN MAX
0.193 0.200
0.169 0.177
−−−
0.047
0.002 0.006
0.020 0.030
0.026 BSC
0.020 0.024
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 BSC
0
_
8
_
SECTION N−N
−W−
C
0.10 (0.004)
−T−
SEATING
PLANE
D
G
H
DETAIL E
SOLDERING FOOTPRINT*
7.06
1
0.36
14X
14X
1.26
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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5
ÉÉÉ
ÇÇÇ
ÉÉÉ
ÇÇÇ
0.65
PITCH
DIMENSIONS: MILLIMETERS
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