Important notice
Dear Customer,
On 7 February 2017 the former NXP Standard Product business became a new company with the
tradename
Nexperia.
Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS
semiconductors with its focus on the automotive, industrial, computing, consumer and wearable
application markets
In data sheets and application notes which still contain NXP or Philips Semiconductors references, use
the references to Nexperia, as shown below.
Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/,
use
http://www.nexperia.com
Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use
salesaddresses@nexperia.com
(email)
Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on
the version, as shown below:
- © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights
reserved
Should be replaced with:
-
© Nexperia B.V. (year). All rights reserved.
If you have any questions related to the data sheet, please contact our nearest sales office via e-mail
or telephone (details via
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Thank you for your cooperation and
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Kind regards,
Team Nexperia
Philips Semiconductors
Product specification
20-bit buffer/line driver, non-inverting, with 30Ω
termination resistors (3-State)
74ALVCH162827
FEATURES
•
Complies with JEDEC standard no. 8-1A.
•
CMOS low power consumption
•
Direct interface with TTL levels
•
Current drive
±
12 mA at 3.0 V
•
MULTIBYTE
TM
flow-through standard pin-out architecture
•
Low inductance multiple V
CC
and GND pins for minimum noise
and ground bounce
DESCRIPTION
The 74ALVCH162827 high-performance CMOS device combines
low static and dynamic power dissipation with high speed and high
output drive.
The 74ALVCH162827 20-bit buffers provide high performance bus
interface buffering for wide data/address paths or buses carrying
parity. They have NAND Output Enables (nOE1, nOE2) for
maximum control flexibility.
The 74ALVCH162827 is designed with 30Ω series resistance in both
the pull-up and pull-down output structures. This design reduces line
noise in applications such as memory address drivers, clock drivers
and bus receivers/transmitters.
To ensure the high impedance state during power up or power
down, OE should be tied to V
CC
through a pullup resistor; the
minimum value of the resistor is determined by the
current-sinking/current-sourcing capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data
inputs at a valid logic level.
•
Integrated 30
W
termination resistors
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25°C; t
r
= t
f
= 2.5ns
SYMBOL
PARAMETER
Propagation delay
t
PHL
/t
PLH
nAn to nYn
C
I
Input capacitance
C
PD
Power dissipation capacitance per latch
dissi ation ca acitance er
CONDITIONS
V
CC
= 2.5V, C
L
= 30pF
V
CC
= 3.3V, C
L
= 50pF
V
I
= GND to V
CC1
Output enabled
Output disabled
TYPICAL
2.9
2.9
5
14
3
UNIT
ns
pF
pF
F
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
mW):
P
D
= C
PD
×
V
CC2
×
f
i
+
S
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacity in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
S
(C
L
×
V
CC2
×
f
o
) = sum of outputs.
ORDERING INFORMATION
PACKAGES
56-Pin Plastic TSSOP Type II
TEMPERATURE RANGE
–40°C to +85°C
OUTSIDE NORTH AMERICA
74ALVCH162827DGG
NORTH AMERICA
ACH162827DGG
DWG NUMBER
SOT364-1
PIN DESCRIPTION
PIN NUMBER
55, 54, 52, 51, 49, 48, 47, 45, 44, 43,
42, 41, 40, 38, 37, 36, 34, 33, 31, 30
2, 3, 5, 6, 8, 9, 10, 12, 13, 14,
15, 16, 17, 19, 20, 21, 23, 24, 26, 27
1, 56,
28, 29
4, 11, 18, 25, 32, 39, 46, 53
7, 22, 35, 50
SYMBOL
1A0 - 1A9
2A0 - 2A9
1Y0 - 1Y9
2Y0 - 2Y9
1OE1 1OE2,
2OE1, 2OE2
GND
V
CC
Data inputs
Data outputs
Output enable inputs (active-LOW)
Ground (0V)
Positive supply voltage
FUNCTION
1998 Sep 29
2
853-2127 20100
Philips Semiconductors
Product specification
20-bit buffer/line driver, non-inverting, with 30Ω
termination resistors (3-State)
74ALVCH162827
LOGIC DIAGRAM
nA0
nA1
nA2
nA3
nA4
nA5
nA6
nA7
nA8
nA9
nOE1
nOE2
nY0
nY1
nY2
nY3
nY4
nY5
nY6
nY7
nY8
nY9
SH00013
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
DC supply voltage 2.5V range (for max. speed
performance @ 30 pF output load)
V
CC
DC supply voltage 3.3V range (for max. speed
performance @ 50 pF output load)
DC Input voltage range
DC output voltage range
Operating free-air temperature range
Input rise and fall times
V
CC
= 2.3 to 3.0V
V
CC
= 3.0 to 3.6V
CONDITIONS
MIN
2.3
3.0
0
0
–40
0
0
MAX
2.7
V
3.6
V
CC
V
CC
+85
20
10
V
V
°C
ns/V
UNIT
V
I
V
O
T
amb
t
r
, t
f
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
GND
, I
CC
T
stg
P
TOT
PARAMETER
DC supply voltage
DC input diode current
DC input voltage
DC output diode current
DC output voltage
DC output source or sink current
DC V
CC
or GND current
Storage temperature range
Power dissipation per package
–plastic thin-medium-shrink (TSSOP)
For temperature range: –40 to +125
°C
above +55°C derate linearly with 8 mW/K
V
I
t0
Note 1
V
O
uV
CC
or V
O
t
0
Note 1
V
O
= 0 to V
CC
CONDITIONS
RATING
–0.5 to +4.6
–50
–0.5 to +4.6
"50
–0.5 to V
CC
+0.5
"50
"100
–65 to +150
600
UNIT
V
mA
V
mA
V
mA
mA
°C
mW
NOTE:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 Sep 29
4
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