S i 5 1 2 / 5 13
D
U A L
F
REQUENCY
C
R Y S TA L
O
SCILLATOR
(X O )
100 k H
Z T O
250 MH
Z
Features
Supports any frequency from
100 kHz to 250 MHz
Two selectable output frequencies
Low-jitter operation
2 to 4 week lead times
Total stability includes 10-year
aging
Comprehensive production test
coverage includes crystal ESR and
DLD
On-chip LDO regulator for power
supply noise filtering
3.3, 2.5, or 1.8 V operation
Differential (LVPECL, LVDS,
HCSL) or CMOS output options
Optional integrated 1:2 CMOS
fanout buffer
Runt suppression on OE and
power on
Industry standard 5x7, 3.2x5, and
2.5x3.2 mm packages
Pb-free, RoHS compliant
–40
to 85
o
C operation
Si5602
2.5x3.2mm
5x7mm and 3.2x5mm
Applications
SONET/SDH/OTN
Gigabit Ethernet
Fibre Channel/SAS/SATA
PCI Express
Ordering Information:
See page 13.
Broadcast video
Switches/routers
Telecom
FPGA/ASIC clock generation
Pin Assignments:
See page 12.
Description
The Si512/513 dual frequency XO utilizes Silicon Laboratories' advanced
PLL technology to provide any frequency from 100 kHz to 250 MHz. Unlike a
traditional XO where a different crystal is required for each output frequency,
the Si512/513 uses one fixed crystal and Silicon Labs’ proprietary any-
frequency synthesizer to generate any frequency across this range. This IC-
based approach allows the crystal resonator to provide enhanced reliability,
improved mechanical robustness, and excellent stability. In addition, this
solution provides superior supply noise rejection, simplifying low jitter clock
generation in noisy environments. The Si512/513 is factory-configurable for a
wide variety of user specifications, including frequency, supply voltage,
output format, output enable polarity, and stability. Specific configurations are
factory-programmed at time of shipment, eliminating long lead times and
non-recurring engineering charges associated with custom frequency
oscillators.
FS
OE
GND
1
2
3
6
5
4
V
DD
NC
CLK
Si512 CMOS Dual XO
OE
FS
GND
1
2
3
6
5
4
V
DD
NC
CLK
Si513 CMOS Dual XO
FS
OE
1
2
3
6
5
4
V
DD
CLK–
CLK+
Functional Block Diagram
V
DD
GND
Si512 LVDS/LVPECL/HCSL/CMOS
Dual XO
OE
FS
GND
1
2
3
6
5
4
V
DD
OE
Fixed
Frequency
Oscillator
Power Supply Filtering
Any-Frequency
0.1 to 250 MHz
DSPLL
®
Synthesis
CLK+
CLK–
CLK–
CLK+
Si513 LVDS/LVPECL/HCSL/CMOS
Dual XO
FS
GND
Rev. 1.2 6/18
Copyright © 2018 by Silicon Laboratories
Si512/13
Si512/513
T
ABLE O F
C
ONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Solder Reflow and Rework Requirements for 2.5x3.2 mm Packages . . . . . . . . . . . . . . 10
3. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1. Dual CMOS Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5. Package Outline Diagram, 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6. PCB Land Pattern: 5 x 7 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
7. Package Outline Diagram: 3.2 x 5.0 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
8. PCB Land Pattern: 3.2 x 5.0 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
9. Package Outline Diagram: 2.5 x 3.2 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
10. PCB Land Pattern: 2.5 x 3.2 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
11. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
11.1. Si512/513 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
11.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2
Rev. 1.2
Si512/513
1. Electrical Specifications
Table 1. Operating Specifications
V
DD
= 1.8 V ±5%, 2.5 or 3.3 V ±10%, T
A
= –40 to +85
o
C
Parameter
Supply Voltage
Symbol
V
DD
Test Condition
3.3 V option
2.5 V option
1.8 V option
Min
2.97
2.25
1.71
—
—
—
—
—
0.80 x V
DD
—
—
–40
Typ
3.3
2.5
1.8
21
19
39
41
—
—
—
45
—
Max
3.63
2.75
1.89
26
23
43
44
18
—
0.20 x V
DD
—
85
Units
V
V
V
mA
Supply Current
I
DD
CMOS, 100 MHz,
single-ended
LVDS
(output enabled)
LVPECL
(output enabled)
HCSL
(output enabled)
Tristate
(output disabled)
mA
mA
mA
mA
V
V
k
o
FS, OE "1" Setting
FS, OE "0" Setting
FS, OE Internal Pull-
Up/Pull-Down Resistor
*
Operating Temperature
V
IH
V
IL
R
I
T
A
See Note
See Note
C
Note:
Active high and active low polarity OE options available. Active high uses internal pull-up. Active low uses internal pull-
down. See ordering information on page 12.
Rev. 1.2
3
Si512/513
Table 2. Output Clock Frequency Characteristics
V
DD
= 1.8 V ±5%, 2.5 or 3.3 V ±10%, T
A
= –40 to +85
o
C
Parameter
Nominal Frequency
Total Stability*
Symbol
F
O
F
O
Test Condition
CMOS, Dual CMOS
LVDS/LVPECL/HCSL
Frequency Stability Grade C
Frequency Stability Grade B
Frequency Stability Grade A
Min
0.1
0.1
–30
–50
–100
–20
–25
–50
—
—
—
—
—
—
Typ
—
—
Max
212.5
250
+30
+50
+100
+20
+25
+50
Units
MHz
MHz
ppm
ppm
ppm
ppm
ppm
ppm
ms
µs
µs
µs
µs
ms
Temperature Stability
Frequency Stability Grade C
Frequency Stability Grade B
Frequency Stability Grade A
Startup Time
Disable Time
Enable Time
Settling Time after FS
Change
T
SU
T
D
T
E
t
FRQ
Minimum V
DD
to output
frequency (F
O
) within specification
F
O
10
MHz
F
O
< 10 MHz
F
O
10
MHz
F
O
< 10 MHz
—
—
—
—
—
—
10
5
40
20
60
10
*Note:
Total stability includes initial accuracy, operating temperature, supply voltage change, load change, shock and
vibration (not under operation), and 10 years aging at 40
°
C.
4
Rev. 1.2
Si512/513
Table 3. Output Clock Levels and Symmetry
V
DD
= 1.8 V ±5%, 2.5 or 3.3 V ±10%, T
A
= –40 to +85
o
C
Parameter
CMOS Output Logic
High
CMOS Output Logic
Low
CMOS Output Logic
High Drive
Symbol
V
OH
V
OL
I
OH
Test Condition
Min
0.85 x V
DD
—
Typ
—
—
—
—
—
—
—
—
0.8
0.6
—
Max
—
0.15 x V
DD
—
—
—
—
—
—
1.2
0.9
565
Units
V
V
mA
mA
mA
mA
mA
mA
ns
ns
ps
3.3 V
2.5 V
1.8 V
–8
–6
–4
8
6
4
—
—
—
CMOS Output Logic
Low Drive
I
OL
3.3 V
2.5 V
1.8 V
CMOS Output Rise/Fall
Time
(20 to 80% V
DD
)
LVPECL/HCSL Output
Rise/Fall Time
(20 to 80% V
DD
)
LVDS Output Rise/Fall
Time
(20 to 80% V
DD
)
LVPECL Output
Common Mode
LVPECL Output Swing
LVDS Output Common
Mode
LVDS Output Swing
HCSL Output Common
Mode
HCSL Output Swing
Duty Cycle
T
R
/T
F
0.1 to 125 MHz,
C
L
= 15 pF
0.1 to 212.5 MHz,
C
L
= no load
T
R
/T
F
T
R
/T
F
—
—
800
ps
V
OC
V
O
V
OC
V
O
V
OC
V
O
DC
50
to V
DD
– 2 V,
single-ended
50
to V
DD
– 2 V,
single-ended
100
line-line, V
DD
= 3.3/2.5 V
100
line-line, V
DD
= 1.8 V
Single-ended, 100
differential
termination
50
to
ground
Single-ended
All Output Formats
—
0.55
1.13
0.83
0.25
0.35
0.58
48
V
DD
–
1.4 V
0.8
1.23
0.92
0.35
0.38
0.73
50
—
0.90
1.33
1.00
0.45
0.42
0.85
52
V
V
PPSE
V
V
V
PPSE
V
V
PPSE
%
Rev. 1.2
5
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
