PD -91535
IRL540NS/L
HEXFET
®
Power MOSFET
Advanced Process Technology
l
Surface Mount (IRL540NS)
l
Low-profile through-hole (IRL540NL)
l
175°C Operating Temperature
l
Fast Switching
l
Fully Avalanche Rated
Description
l
D
V
DSS
= 100V
G
S
R
DS(on)
= 0.044Ω
I
D
= 36A
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve
extremely low on-resistance per silicon area. This
benefit, combined with the fast switching speed and
ruggedized device design that HEXFET Power MOSFETs
are well known for, provides the designer with an extremely
efficient and reliable device for use in a wide variety of
applications.
The D
2
Pak is a surface mount power package capable of
accommodating die sizes up to HEX-4. It provides the
highest power capability and the lowest possible on-
resistance in any existing surface mount package. The
D
2
Pak is suitable for high current applications because of
its low internal connection resistance and can dissipate up
to 2.0W in a typical surface mount application.
The through-hole version (IRF540NL) is available for low-
profile applications.
D 2 P ak
T O -26 2
Absolute Maximum Ratings
Parameter
I
D
@ T
C
= 25°C
I
D
@ T
C
= 100°C
I
DM
P
D
@T
A
= 25°C
P
D
@T
C
= 25°C
V
GS
E
AS
I
AR
E
AR
dv/dt
T
J
T
STG
Continuous Drain Current, V
GS
@ 10V
Continuous Drain Current, V
GS
@ 10V
Pulsed Drain Current
Power Dissipation
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Max.
36
26
120
3.8
140
0.91
± 16
310
18
14
5.0
-55 to + 175
300 (1.6mm from case )
Units
A
W
W
W/°C
V
mJ
A
mJ
V/ns
°C
Thermal Resistance
Parameter
R
θJC
R
θJA
Junction-to-Case
Junction-to-Ambient ( PCB Mounted,steady-state)**
Typ.
–––
–––
Max.
1.1
40
Units
°C/W
5/13/98
IRL540NS/L
Electrical Characteristics @ T
J
= 25°C (unless otherwise specified)
V
(BR)DSS
∆V
(BR)DSS
/∆T
J
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Forward Transconductance
Drain-to-Source Leakage Current
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Internal Source Inductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
R
DS(on)
V
GS(th)
g
fs
I
DSS
I
GSS
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
L
S
C
iss
C
oss
C
rss
Min.
100
–––
–––
–––
–––
1.0
14
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Max. Units
Conditions
–––
V
V
GS
= 0V, I
D
= 250µA
––– V/°C Reference to 25°C, I
D
= 1mA
0.044
V
GS
= 10V, I
D
= 18A
0.053
Ω
V
GS
= 5.0V, I
D
= 18A
0.063
V
GS
= 4.0V, I
D
= 15A
2.0
V
V
DS
= V
GS
, I
D
= 250µA
–––
S
V
DS
= 25V, I
D
= 18A
25
V
DS
= 100V, V
GS
= 0V
A
250
V
DS
= 80V, V
GS
= 0V, T
J
= 150°C
100
V
GS
= 16V
nA
-100
V
GS
= -16V
74
I
D
= 18A
9.4
nC V
DS
= 80V
38
V
GS
= 5.0V, See Fig. 6 and 13
–––
V
DD
= 50V
–––
I
D
= 18A
ns
–––
R
G
= 5.0Ω, V
GS
= 5.0V
–––
R
D
= 2.7Ω, See Fig. 10
Between lead,
7.5 –––
nH
and center of die contact
1800 –––
V
GS
= 0V
350 –––
pF
V
DS
= 25V
170 –––
ƒ = 1.0MHz, See Fig. 5
Typ.
–––
0.11
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
11
81
39
62
Source-Drain Ratings and Characteristics
I
S
I
SM
V
SD
t
rr
Q
rr
t
on
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
36
––– –––
showing the
A
G
integral reverse
––– ––– 120
S
p-n junction diode.
––– ––– 1.3
V
T
J
= 25°C, I
S
= 18A, V
GS
= 0V
––– 190 290
ns
T
J
= 25°C, I
F
= 18A
––– 1.1 1.7
µC di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by L
S
+L
D
)
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
Pulse width
≤
300µs; duty cycle
≤
2%.
Uses IRL540N data and test conditions
Starting T
J
= 25°C, L = 1.9mH
R
G
= 25Ω, I
AS
= 18A. (See Figure 12)
I
SD
≤
18A, di/dt
≤
180A/µs, V
DD
≤
V
(BR)DSS
,
T
J
≤
175°C
** When mounted on 1" square PCB ( FR-4 or G-10 Material ).
For recommended soldering techniques refer to application note #AN-994.
IRL540NS/L
1000
TOP
VGS
15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
1000
TOP
I
D
, Drain-to-Source Current (A)
100
I
D
, Drain-to-Source Current (A)
VGS
15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
100
10
10
2.5V
2.5V
1
0.1
1
20µs PULSE WIDTH
T
J
= 25°C
10
100
A
1
0.1
1
20µs PULSE WIDTH
T
J
= 175°C
10
100
A
V
D S
, Drain-to-Source Voltage (V)
V
D S
, Drain-to-Source Voltage (V)
Fig 1.
Typical Output Characteristics
Fig 2.
Typical Output Characteristics
1000
3.0
R
D S ( o n )
, Drain-to-Source On Resistance
(Normalized)
I
D
= 30A
I
D
, Drain-to-Source Current (A)
2.5
100
T
J
= 25°C
T
J
= 175°C
2.0
1.5
10
1.0
0.5
1
V
D S
= 50V
20µs PULSE WIDTH
2
4
6
8
10
A
0.0
-60
-40
-20
0
20
40
60
80
V
G S
= 10V
100 120 140 160 180
A
V
G S
, Gate-to-Source Voltage (V)
T
J
, Junction Temperature (°C)
Fig 3.
Typical Transfer Characteristics
Fig 4.
Normalized On-Resistance
Vs. Temperature
IRL540NS/L
3000
V
G S
, Gate-to-Source Voltage (V)
V
G S
= 0V,
f = 1MHz
C
iss
= C
gs
+ C
gd
C SHORTED
,
ds
C
rss
= C
gd
C
oss
= C
ds
+ C
gd
15
I
D
= 18A
V
D S
= 80V
V
D S
= 50V
V
D S
= 20V
12
C, Capacitance (pF)
C
iss
2000
9
6
1000
C
oss
C
rss
3
0
1
10
100
A
0
0
20
40
FOR TEST CIRCUIT
SEE FIGURE 13
60
80
100
A
V
D S
, Drain-to-Source Voltage (V)
Q
G
, Total Gate Charge (nC)
Fig 5.
Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 6.
Typical Gate Charge Vs.
Gate-to-Source Voltage
1000
1000
I
S D
, Reverse Drain Current (A)
OPERATION IN THIS AREA LIMITED
BY R
D S ( o n )
100
I
D
, Drain Current (A)
100
10µs
T
J
= 175°C
T
J
= 25°C
10
100µs
10
1ms
1
0.4
0.6
0.8
1.0
1.2
1.4
V
G S
= 0V
1.6
A
1
1
T
C
= 25°C
T
J
= 175°C
Single Pulse
10
10ms
A
100
1000
1.8
V
S D
, Source-to-Drain Voltage (V)
V
D S
, Drain-to-Source Voltage (V)
Fig 7.
Typical Source-Drain Diode
Forward Voltage
Fig 8.
Maximum Safe Operating Area
IRL540NS/L
40
V
DS
V
GS
R
D
D.U.T.
+
I
D
, Drain Current (A)
30
R
G
-
V
DD
5.0V
20
Pulse Width
≤ 1
µs
Duty Factor
≤ 0.1 %
Fig 10a.
Switching Time Test Circuit
10
V
DS
90%
0
25
50
75
100
125
150
175
T
C
, Case Temperature ( °C)
10%
V
GS
Fig 9.
Maximum Drain Current Vs.
Case Temperature
t
d(on)
t
r
t
d(off)
t
f
Fig 10b.
Switching Time Waveforms
10
Thermal Response (Z
thJC
)
1
D = 0.50
0.20
0.10
0.1
0.05
0.02
0.01
SINGLE PULSE
(THERMAL RESPONSE)
Notes:
1. Duty factor D = t
1
/ t
2
2. Peak T
J
= P
DM
x Z
thJC
+ T
C
0.0001
0.001
0.01
0.1
1
P
DM
t
1
t
2
0.01
0.00001
t
1
, Rectangular Pulse Duration (sec)
Fig 11.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
FPGA/CPLD
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