74AXP1G58
Low-power configurable multiple function gate
Rev. 3 — 16 September 2015
Product data sheet
1. General description
The 74AXP1G58 is a configurable multiple function gate with Schmitt-trigger inputs. The
device can be configured as any of the following logic functions AND, OR, NAND, NOR,
XOR, inverter and buffer. All inputs can be connected directly to V
CC
or GND.
This device ensures very low static and dynamic power consumption across the entire
V
CC
range from 0.7 V to 2.75 V. This device is fully specified for partial power-down
applications using I
OFF
. The I
OFF
circuitry disables the output, preventing the potentially
damaging backflow current through the device when it is powered down.
2. Features and benefits
Wide supply voltage range from 0.7 V to 2.75 V
Low input capacitance; C
I
= 0.5 pF (typical)
Low output capacitance; C
O
= 1.0 pF (typical)
Low dynamic power consumption; C
PD
= 2.7 pF at V
CC
= 1.2 V (typical)
Low static power consumption; I
CC
= 0.6
A
(85
C
maximum)
High noise immunity
Complies with JEDEC standard:
JESD8-12A.01 (1.1 V to 1.3 V)
JESD8-11A.01 (1.4 V to 1.6 V)
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A.01 (2.3 V to 2.7 V)
ESD protection:
HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2 kV
CDM JESD22-C101E exceeds 1000 V
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 2.75 V
Low noise overshoot and undershoot < 10% of V
CC
I
OFF
circuitry provides partial power-down mode operation
Multiple package options
Specified from
40 C
to +85
C
Nexperia
74AXP1G58
Low-power configurable multiple function gate
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74AXP1G58GM
74AXP1G58GN
74AXP1G58GS
74AXP1G58GX
40 C
to +85
C
40 C
to +85
C
40 C
to +85
C
40 C
to +85
C
Name
XSON6
XSON6
XSON6
X2SON6
Description
Version
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1
1.45
0.5 mm
extremely thin small outline package; no leads;
6 terminals; body 0.9
1.0
0.35 mm
extremely thin small outline package; no leads;
6 terminals; body 1.0
1.0
0.35 mm
plastic thermal extremely thin small outline package;
no leads; 6 terminals; body 1
0.8
0.35 mm
SOT1115
SOT1202
SOT1255
Type number
4. Marking
Table 2.
Marking codes
Marking code
[1]
RK
RK
RK
RK
Type number
74AXP1G58GM
74AXP1G58GN
74AXP1G58GS
74AXP1G58GX
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
Fig 1.
Logic symbol
74AXP1G58
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 16 September 2015
2 of 18
Nexperia
74AXP1G58
Low-power configurable multiple function gate
6. Pinning information
6.1 Pinning
Fig 2.
Pin configuration SOT886
Fig 3.
Pin configuration SOT1115
and SOT1202
Fig 4.
Pin configuration SOT1255
(X2SON6)
6.2 Pin description
Table 3.
Symbol
B
GND
A
Y
V
CC
C
Pin description
Pin
1
2
3
4
5
6
Description
data input
ground (0 V)
data input
data output
supply voltage
data input
7. Functional description
Table 4.
Input
C
L
L
L
L
H
H
H
H
[1]
Function table
[1]
Output
B
L
L
H
H
L
L
H
H
A
L
H
L
H
L
H
L
H
Y
L
H
L
H
H
H
L
L
H = HIGH voltage level; L = LOW voltage level.
74AXP1G58
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 16 September 2015
3 of 18
Nexperia
74AXP1G58
Low-power configurable multiple function gate
7.1 Logic configurations
Table 5.
Function selection table
Figure
see
Figure 5
see
Figure 8
see
Figure 6
and
Figure 7
see
Figure 6
and
Figure 7
see
Figure 8
see
Figure 5
see
Figure 9
see
Figure 10
see
Figure 11
Logic function
2-input NAND
2-input NAND with both inputs inverted
2-input AND with inverted input
2-input NOR with inverted input
2-input OR
2-input OR with both inputs inverted
2-input XOR
Buffer
Inverter
Fig 5.
2-input NAND gate or 2-input OR gate with
both inputs inverted
Fig 6.
2-input AND gate with inverted B input or
2-input NOR gate with inverted C input
Fig 7.
2-input AND gate with inverted C input or
2-input NOR gate with inverted A input
Fig 8.
2-input OR gate or 2-input NAND gate with
both inputs inverted
Fig 9.
2-input XOR gate
Fig 10. Buffer
74AXP1G58
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 16 September 2015
4 of 18
Nexperia
74AXP1G58
Low-power configurable multiple function gate
Fig 11. Inverter
8. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
< 0 V
[1]
Min
0.5
50
0.5
50
[1]
Max
+3.3
-
+3.3
-
+3.3
20
50
-
+150
250
Unit
V
mA
V
mA
V
mA
mA
mA
C
mW
V
O
< 0 V
V
O
= 0 V to V
CC
0.5
-
-
50
65
T
amb
=
40 C
to +85
C
-
The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
9. Recommended operating conditions
Table 7.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
O
T
amb
Parameter
supply voltage
input voltage
output voltage
ambient temperature
active mode
power-down mode; V
CC
= 0 V
Conditions
Min
0.7
0
0
0
40
Max
2.75
2.75
V
CC
2.75
+85
Unit
V
V
V
V
C
74AXP1G58
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 16 September 2015
5 of 18
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