PCA9629
Fm+ I
2
C-bus stepper motor controller
Rev. 1 — 29 February 2012
Product data sheet
1. General description
The PCA9629 is an I
2
C-bus controlled low-power CMOS device that provides all the logic
and control required to drive a four phase stepper motor. PCA9629 is intended to be used
with external high current drivers to drive the motor coils. The PCA9629 supports three
stepper motor drive formats: one-phase (wave drive), two-phase, and half-step. In
addition, when used as inputs, four General Purpose Input/Outputs (GPIOs) allow sensing
of logic level output from optical interrupter modules and generate active LOW interrupt
signal on the INT pin of PCA9629. This is a useful feature in sensing home position of
motor shaft or reference for step pulses. Upon interrupt, the PCA9629 can be
programmed to automatically stop the motor or reverse the direction of rotation of motor.
Output wave train is programmable using control registers. The control registers are
programmed via the I
2
C-bus. Features built into the PCA9629 provide highly flexible
control of stepper motor, off-load bus master/micro and significantly reduce I
2
C-bus traffic.
These include control of step size, number of steps per single command, number of full
rotations and direction of rotation. A ramp-up on start and/or ramp-down on stop is also
provided.
The PCA9629 is available in a 16-pin TSSOP package and is specified over the
40 C
to
+85
C
industrial temperature range.
2. Features and benefits
Generate motor coil drive phase sequence signals with four outputs for use with
external high current drivers to off-load CPU
Four balanced push-pull type outputs capable of sinking 25 mA or sourcing 25 mA for
glueless connection to external high current drivers needed to drive motor coils
Up to 1000 pF loads with 100 ns rise and fall times
Built-in oscillator requires no external components
Stepper motor drive control logic
One-phase (wave drive), two-phase, and half-step drive format logic level outputs
Programmable step rate: 344.8 kpps to 0.3 pps with
5
% accuracy
Programmable ramp-up on start and ramp-down to stop
Programmable steps and rotation control
Sensor enabled drive control: linked to interrupt from I/O pins
Direction control of motor shaft
Selectable active hold, power off or released states for motor shaft
NXP Semiconductors
PCA9629
Fm+ I
2
C-bus stepper motor controller
Four general purpose I/Os:
Configured to sense logic level outputs from optical interrupter photo transistor
circuit
Configured as outputs to drive (source/sink) LEDs or other loads up to 25 mA
Programmable interrupt Mask Control for input pins
4.5 V to 5.5 V operation
1 MHz Fast-mode Plus (Fm+) I
2
C-bus serial interface with 30 mA high drive capability
on SDA output for driving high capacitive buses
Compliant with I
2
C-bus Standard-mode (100 kHz) and Fast-mode (400 kHz) speeds
Active LOW open-drain interrupt output
Active LOW reset (RESET) input pin resets device to power-up default state: can be
used to recover from bus stuck condition
Programmable watchdog timer
All Call address allows programming of more than one device at the same time with
the same parameters
16 programmable slave addresses using two address pins
40 C
to +85
C
operation
ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22C101
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
Package offered: TSSOP16
3. Applications
Amusement machines
Gaming and slot machines
Consumer home appliances or toys
Industrial automation
HVAC and building climate control systems
Robotics
4. Ordering information
Table 1.
Ordering information
Package
Name
PCA9629PW
TSSOP16
Description
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
Version
SOT403-1
Type number
4.1 Ordering options
Table 2.
Ordering options
Topside mark
PCA9629
Temperature range
T
amb
=
40 C
to +85
C
Type number
PCA9629PW
PCA9629
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 29 February 2012
2 of 51
NXP Semiconductors
PCA9629
Fm+ I
2
C-bus stepper motor controller
5. Block diagram
AD0 AD1
PCA9629
SCL
SDA
I
2
C-BUS
CONTROL
V
DD
200 kΩ
INPUT
REGISTER
INPUT FILTER
GPIO AND
INTERRUPT
OUTPUT
CONTROL
GPIO
P0
P3
POWER-ON
RESET
INT
RESET
V
SS
OSCILLATOR
WATCHDOG
TIMER
CONTROL
REGISTERS
MOTOR CONTROLLER
INTERRUPT
HANDLER
RAMP
CONTROL
LOOP DELAY
TIMER
OUT0
STEPS,
ROTATIONS
AND
PULSE WIDTH
COUNTERS
COIL
EXCITATION
LOGIC
OUTPUT
PHASE
SEQUENCE
GENERATOR
OUT3
002aad902
Remark:
All I/Os are set to inputs at power-up and reset.
Fig 1.
PCA9629 block diagram
PCA9629
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 29 February 2012
3 of 51
NXP Semiconductors
PCA9629
Fm+ I
2
C-bus stepper motor controller
6. Pinning information
6.1 Pinning
P0
P1
P2
P3
AD0
AD1
RESET
V
SS
1
2
3
4
5
6
7
8
002aad903
16 V
DD
15 SDA
14 SCL
13 INT
12 OUT0
11 OUT1
10 OUT2
9
OUT3
PCA9629PW
Fig 2.
Pin configuration for TSSOP16
6.2 Pin description
Table 3.
Symbol
P0
P1
P2
P3
AD0
AD1
RESET
V
SS
OUT3
OUT2
OUT1
OUT0
INT
SCL
SDA
V
DD
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Type
I/O
I/O
I/O
I/O
I
I
I
ground
O
O
O
O
O
I
I/O
power supply
Description
input/output 0 (output is 25 mA push-pull)
input/output 1 (output is 25 mA push-pull)
input/output 2 (output is 25 mA push-pull)
input/output 3 (output is 25 mA push-pull)
address input 0
address input 1
active LOW reset input with 1
s
filter
supply ground
control 25 mA push-pull output 3
control 25 mA push-pull output 2
control 25 mA push-pull output 1
control 25 mA push-pull output 0
active LOW interrupt output; open-drain
serial clock line
serial data line; open-drain capable of sinking 30 mA
supply voltage
PCA9629
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 29 February 2012
4 of 51
NXP Semiconductors
PCA9629
Fm+ I
2
C-bus stepper motor controller
7. Functional description
Refer to
Figure 1 “PCA9629 block diagram”.
7.1 Device address
Following a START condition, the bus master must send the target slave address followed
by a read or write operation. The slave address of the PCA9629 is shown in
Figure 3.
Slave address pins AD1 and AD0 choose one of 16 slave addresses. To conserve power,
no internal pull-up resistors are incorporated on AD1 and AD0.
Table 4
shows all 16 slave
addresses by connecting the AD0 and AD1 to V
DD
, V
SS
, SCL or SDA.
slave address
0
1
fixed
0
A3
A2
A1
A0 R/W
programmable
002aad905
Fig 3.
PCA9629 device address
The last bit of the first byte defines the reading from or writing to the PCA9629. When set
to logic 1 a read is selected, while logic 0 selects a write operation.
Table 4.
AD1
PCA9629 address map
AD0
Device family high-order Variable portion of address
address bits
A6
V
SS
V
SS
V
DD
V
DD
V
SS
V
SS
V
DD
V
DD
SCL
SDA
SCL
SDA
SCL
SCL
SDA
SDA
V
SS
V
DD
V
SS
V
DD
SCL
SDA
SCL
SDA
V
SS
V
SS
V
DD
V
DD
SCL
SDA
SCL
SDA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
40h
42h
44h
46h
48h
4Ah
4Ch
4Eh
50h
52h
54h
56h
58h
5Ah
5Ch
5Eh
Address
PCA9629
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 29 February 2012
5 of 51
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