74LV4052
Dual 4-channel analog multiplexer/demultiplexer
Rev. 4 — 1 July 2013
Product data sheet
1. General description
The 74LV4052 is a low-voltage CMOS device and is pin and function compatible with the
74HC/HCT4052.
The 74LV4052 is a dual 4-channel analog multiplexer/demultiplexer with a common select
logic. Each multiplexer has four independent inputs/outputs (nY0 to nY3) and a common
input/output (nZ). The common channel select logics include two digital select inputs (S0
and S1) and an active LOW enable input (E). With E LOW, one of the four switches is
selected (low impedance ON-state) by S0 and S1. With E HIGH, all switches are in the
high impedance OFF-state, independent of S0 and S1. V
CC
and GND are the supply
voltage pins for the digital control inputs (S0, S1 and E). The V
CC
to GND ranges are 1.0 V
to 6.0 V. The analog inputs/outputs (nY0, to nY3, and nZ) can swing between V
CC
as a
positive limit and V
EE
as a negative limit. V
CC
- V
EE
may not exceed 6.0 V. For operation
as a digital multiplexer/demultiplexer, V
EE
is connected to GND (typically ground).
2. Features and benefits
Optimized for low-voltage applications: 1.0 V to 6.0 V
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
Low ON resistance:
145
(typical) at V
CC
V
EE
= 2.0 V
90
(typical) at V
CC
V
EE
= 3.0 V
60
(typical) at V
CC
V
EE
= 4.5 V
Logic level translation:
To enable 3 V logic to communicate with
3
V analog signals
Typical ‘break before make’ built in
ESD protection:
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from
40 C
to +85
C
and from
40 C
to +125
C
NXP Semiconductors
74LV4052
Dual 4-channel analog multiplexer/demultiplexer
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LV4052N
74LV4052D
74LV4052DB
74LV4052PW
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
Name
DIP16
SO16
SSOP16
TSSOP16
Description
plastic dual in-line package; 16 leads (300 mil)
plastic small outline package; 16 leads; body
width 3.9 mm
plastic shrink small outline package; 16 leads; body
width 5.3 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
Version
SOT38-4
SOT109-1
SOT338-1
SOT403-1
Type number
4. Functional diagram
Fig 1.
74LV4052
Functional diagram
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 1 July 2013
2 of 26
NXP Semiconductors
74LV4052
Dual 4-channel analog multiplexer/demultiplexer
10
13
1Z
1Y0
10
9
S0
S1
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
6
E
2Z
001aah824
0
1
G4
4
×
9
6
12
14
15
11
1
5
2
4
13
3
0
3
MDX
0
1
2
3
1
5
2
4
12
14
15
11
001aah825
2Y3
3
Fig 2.
Logic symbol
Fig 3.
IEC logic symbol
nYn
V
CC
V
EE
V
CC
V
CC
V
CC
from
logic
V
EE
nZ
V
EE
mnb043
Fig 4.
Schematic diagram (one switch)
74LV4052
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 1 July 2013
3 of 26
NXP Semiconductors
74LV4052
Dual 4-channel analog multiplexer/demultiplexer
5. Pinning information
5.1 Pinning
Fig 5.
Pin configuration for DIP16 andSO16
Fig 6.
Pin configuration for (T)SSOP16
5.2 Pin description
Table 2.
Symbol
2Y0
2Y2
2Z
2Y3
2Y1
E
V
EE
GND
S1
S0
1Y3
1Y0
1Z
1Y1
1Y2
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Description
independent input or output
independent input or output
common input or output
independent input or output
independent input or output
enable input (active LOW)
negative supply voltage
ground (0 V)
select logic input
select logic input
independent input or output
independent input or output
common input or output
independent input or output
independent input or output
positive supply voltage
74LV4052
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 1 July 2013
4 of 26
NXP Semiconductors
74LV4052
Dual 4-channel analog multiplexer/demultiplexer
6. Functional description
Table 3.
Input
E
L
L
L
L
H
[1]
Function table
[1]
Channel on
S1
L
L
H
H
X
S0
L
H
L
H
X
nY0 and nZ
nY1 and nZ
nY2 and nZ
nY3 and nZ
none
H = HIGH voltage level; L = LOW voltage level; X = don’t care.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to V
SS
= 0 V (ground).
Symbol
V
CC
I
IK
I
SK
I
SW
T
stg
P
tot
Parameter
supply voltage
input clamping current
switch clamping current
switch current
storage temperature
total power dissipation
T
amb
=
40 C
to +125
C
DIP16 package
SO16 package
SSOP16 and TSSOP16 package
[1]
[3]
Conditions
[1]
Min
0.5
-
-
-
65
-
-
-
[2]
[2]
[2]
Max
+7.0
20
20
25
+150
750
500
400
Unit
V
mA
mA
mA
C
mW
mW
mW
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
SW
<
0.5
V or V
SW
> V
CC
+ 0.5 V
V
SW
>
0.5
V or V
SW
< V
CC
+ 0.5 V;
source or sink current
To avoid drawing V
CC
current out of terminal nZ, when switch current flows into terminals nYn, the voltage drop across the bidirectional
switch must not exceed 0.4 V. If the switch current flows into terminal nZ, no V
CC
current flows out of terminals nYn. In this case, there is
no limit for the voltage drop across the switch, but the voltages at nYn and nZ may not exceed V
CC
or V
EE
.
The minimum input voltage rating may be exceeded if the input current rating is observed.
For DIP16 package: above 70
C
the value of P
tot
derates linearly with 12 mW/K.
For SO16 package: above 70
C
the value of P
tot
derates linearly with 8 mW/K.
For SSOP16 and TSSOP16 packages: above 60
C
the value of P
tot
derates linearly with 5.5 mW/K.
[2]
[3]
74LV4052
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 1 July 2013
5 of 26
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