74HC299; 74HCT299
8-bit universal shift register; 3-state
Rev. 03 — 28 July 2008
Product data sheet
1. General description
The 74HC299; 74HCT299 are high-speed Si-gate CMOS devices which are
pin-compatible with Low-power Schottky TTL (LSTTL) devices. They are specified in
compliance with JEDEC standard no. 7A.
The 74HC299; 74HCT299 contain eight edge-triggered D-type flip-flops and the
interstage logic necessary to perform synchronous shift-right, shift-left, parallel load and
hold operations. An operation is determined by the mode select inputs S0 and S1, as
shown in
Table 3.
Pins I/O0 to I/O7 are flip-flop 3-state buffer outputs which allow them to operate as data
inputs in parallel load mode. The serial outputs Q0 and Q7 are used for expansion in
serial shifting of longer words.
A LOW signal on the asynchronous master reset input MR overrides the Sn and clock CP
inputs and resets the flip-flops. All other state changes are initiated by the rising edge of
the clock pulse. Inputs can change when the clock is in either state, provided that the
recommended set-up and hold times are observed.
A HIGH signal on the 3-state output enable inputs OE1 or OE2 disables the 3-state
buffers and the I/On outputs are set to the high-impedance OFF-state. In this condition,
the shift, hold, load and reset operations still occur when preparing for a parallel load
operation. The 3-state buffers are also disabled by HIGH signals on both S0 and S1.
2. Features
I
Multiplexed inputs/outputs provide improved bit density
I
Four operating modes:
N
Shift left
N
Shift right
N
Hold (store)
N
Load data
I
Operates with output enable or at high-impedance OFF-state (Z)
I
3-state outputs drive bus lines directly
I
Cascadable for n-bit word lengths
I
ESD protection:
N
HBM JESD22-A114E exceeds 2000 V
N
MM JESD22-A115-A exceeds 200 V
I
Specified from
−40 °C
to +85
°C
and from
−40 °C
to +125
°C
NXP Semiconductors
74HC299; 74HCT299
8-bit universal shift register; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC299
74HC299D
74HC299DB
74HC299N
74HC299PW
74HCT299
74HCT299D
74HCT299DB
74HCT299N
74HCT299PW
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
SO20
SSOP20
DIP20
TSSOP20
plastic small outline package; 20 leads; body
width 7.5 mm
plastic shrink small outline package; 20 leads;
body width 5.3 mm
plastic dual in-line package; 20 leads (300 mil)
SOT163-1
SOT339-1
SOT146-1
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
SO20
SSOP20
DIP20
TSSOP20
plastic small outline package; 20 leads; body
width 7.5 mm
plastic shrink small outline package; 20 leads;
body width 5.3 mm
plastic dual in-line package; 20 leads (300 mil)
SOT163-1
SOT339-1
SOT146-1
Name
Description
Version
Type number
plastic thin shrink small outline package; 20 leads; SOT360-1
body width 4.4 mm
plastic thin shrink small outline package; 20 leads; SOT360-1
body width 4.4 mm
4. Functional diagram
1
DSR
CP
MR
Q0
OE1
OE2
INPUT/3-STATE OUTPUT CIRCUITRY
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
7
13
6
14
5
15
4
16
001aai460
19
S0
S1
DSL
11
12
9
8
2
3
18
8-BIT SHIFT REGISTER
Q7
17
Fig 1.
Functional diagram
74HC_HCT299_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 28 July 2008
2 of 24
NXP Semiconductors
74HC299; 74HCT299
8-bit universal shift register; 3-state
9
2
3
1
19
12
11
7
13
6
14
5
15
4
16
18
R
&
SRG8
3EN5
0
0
M
3
1
C4/1 /2
1, 4D
3, 4D
6, 5
3, 4D
5
1
19
11
18
S0
S1
DSR
DSL
I/O0
I/O1
I/O2
I/O3
I/O4
7
13
6
14
5
15
4
16
8
17
Z6
8
12
9
2
3
CP
MR
I/O5
I/O6
I/O7
OE
Q0
Q7
3, 4D
7, 5
2, 4D
Z7
17
001aai458
001aai459
Fig 2.
Logic symbol
Fig 3.
IEC logic symbol
74HC_HCT299_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 28 July 2008
3 of 24
NXP Semiconductors
74HC299; 74HCT299
8-bit universal shift register; 3-state
DSR
S0
S1
D
Q
CP
FF0
RD
I/O0
CP
Q0
D
Q
CP
FF1
RD
I/O1
OE1
OE2
D
Q
CP
FF2
RD
I/O2
D
Q
CP
FF3
RD
I/O3
D
Q
CP
FF4
RD
I/O4
D
Q
CP
FF5
RD
I/O5
D
Q
CP
FF6
RD
I/O6
DSL
D
Q
CP
FF7
RD
I/O7
Q7
MR
001aai461
Fig 4.
Logic diagram
74HC_HCT299_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 28 July 2008
4 of 24
NXP Semiconductors
74HC299; 74HCT299
8-bit universal shift register; 3-state
5. Pinning information
5.1 Pinning
74HC299
74HCT299
S0
1
2
3
4
5
6
7
8
9
20 V
CC
19 S1
18 DSL
17 Q7
16 I/O7
15 I/O5
14 I/O3
13 I/O1
12 CP
11 DSR
001aai457
74HC299
74HCT299
S0
OE1
OE2
I/O6
I/O4
I/O2
I/O0
Q0
MR
1
2
3
4
5
6
7
8
9
20 V
CC
19 S1
18 DSL
17 Q7
16 I/O7
15 I/O5
14 I/O3
13 I/O1
12 CP
11 DSR
001aai511
OE1
OE2
I/O6
I/O4
I/O2
I/O0
Q0
MR
GND 10
GND 10
Fig 5.
Pin configuration (SO20 and (T)SSOP20)
Fig 6.
Pin configuration (DIP20)
5.2 Pin description
Table 2.
Symbol
S0
OE1
OE2
I/O6
I/O4
I/O2
I/O0
Q0
MR
GND
DSR
CP
I/O1
I/O3
I/O5
I/O7
Q7
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Description
mode select input
3-state output enable input (active LOW)
3-state output enable input (active LOW)
parallel data input or 3-state parallel output (bus driver)
parallel data input or 3-state parallel output (bus driver)
parallel data input or 3-state parallel output (bus driver)
parallel data input or 3-state parallel output (bus driver)
serial output (standard output)
asynchronous master reset input (active LOW)
ground (0 V)
serial data shift-right input
clock input (LOW to HIGH, edge-triggered)
parallel data input or 3-state parallel output (bus driver)
parallel data input or 3-state parallel output (bus driver)
parallel data input or 3-state parallel output (bus driver)
parallel data input or 3-state parallel output (bus driver)
serial output (standard output)
74HC_HCT299_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 28 July 2008
5 of 24
模拟电子
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
