DISCRETE SEMICONDUCTORS
DATA SHEET
BF904A; BF904AR; BF904AWR
N-channel dual gate MOS-FETs
Product specification
Supersedes data of 1999 Feb 01
1999 May 14
Philips Semiconductors
Product specification
N-channel dual gate MOS-FETs
FEATURES
•
Specially designed for use at 5 V
supply voltage
•
Short channel transistor with high
transfer admittance to input
capacitance ratio
•
Low noise gain controlled amplifier
up to 1 GHz
•
Superior cross-modulation
performance during AGC.
APPLICATIONS
•
VHF and UHF applications with
3 to 7 V supply voltage such as
television tuners and professional
communications equipment.
DESCRIPTION
Enhancement type field-effect
transistors. The transistors consist of
an amplifier MOS-FET with source
and substrate interconnected and an
internal bias circuit to ensure good
cross-modulation performance during
AGC.
The BF904A, BF904AR and
BF904AWR are encapsulated in the
SOT143B, SOT143R and SOT343R
plastic packages respectively.
QUICK REFERENCE DATA
SYMBOL
V
DS
I
D
P
tot
y
fs
C
ig1-ss
C
rss
F
T
j
PARAMETER
drain-source voltage
drain current
total power dissipation
forward transfer admittance
input capacitance at gate 1
reverse transfer capacitance
noise figure
operating junction temperature
CAUTION
f = 1 MHz
f = 800 MHz
T
s
≤
110
°C
2
Top view
BF904A; BF904AR; BF904AWR
PINNING
PIN
1
2
3
4
DESCRIPTION
source
drain
gate 2
gate 1
1
Top view
2
MSB014
handbook, 2 columns
4
3
BF904A marking code:
M41.
Fig.1
Simplified outline
(SOT143B).
handbook, 2 columns
3
4
halfpage
3
4
1
2
MSB035
1
MSB842
Top view
BF904AR marking code:
M42.
BF904AWR marking code:
MH.
Fig.2
Simplified outline
(SOT143R).
Fig.3
Simplified outline
(SOT343R).
CONDITIONS
MIN.
−
−
−
22
−
−
−
−
TYP.
−
−
−
25
2.2
25
2
−
MAX.
7
30
200
30
2.6
35
−
150
UNIT
V
mA
mW
mS
pF
fF
dB
°C
This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport
and handling. For further information, refer to Philips specs.: SNW-EQ-608, SNW-FQ-302A and SNW-FQ-302B.
1999 May 14
2
Philips Semiconductors
Product specification
N-channel dual gate MOS-FETs
BF904A; BF904AR; BF904AWR
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
V
DS
I
D
I
G1
I
G2
P
tot
T
stg
T
j
Note
1. T
s
is the temperature of the soldering point of the source lead.
PARAMETER
drain-source voltage
drain current
gate 1 current
gate 2 current
total power dissipation
storage temperature
operating junction temperature
T
s
≤
110
°C;
note 1; see Fig.4
CONDITIONS
−
−
−
−
−
−65
−
MIN.
7
30
±10
±10
200
+150
150
MAX.
V
mA
mA
mA
mW
°C
°C
UNIT
MGL615
handbook, halfpage
250
Ptot
(mW)
200
150
100
50
0
0
50
100
150
Ts (°C)
200
Fig.4 Power derating curve.
1999 May 14
3
Philips Semiconductors
Product specification
N-channel dual gate MOS-FETs
THERMAL CHARACTERISTICS
SYMBOL
R
th j-s
Note
1. Soldering point of the source lead.
STATIC CHARACTERISTICS
T
j
= 25
°C
unless otherwise specified.
SYMBOL
V
(BR)G1-SS
V
(BR)G2-SS
V
(F)S-G1
V
(F)S-G2
V
G1-S(th)
V
G2-S(th)
I
DSX
I
G1-SS
I
G2-SS
Note
1. R
G1
connects gate 1 to V
GG
= 5 V; see Fig.21.
PARAMETER
gate 1-source breakdown voltage
gate 2-source breakdown voltage
forward source-gate 1 voltage
forward source-gate 2 voltage
gate 1-source threshold voltage
gate 2-source threshold voltage
drain-source current
gate 1 cut-off current
gate 2 cut-off current
PARAMETER
thermal resistance from junction to soldering point
BF904A; BF904AR; BF904AWR
CONDITIONS
note 1
VALUE
200
UNIT
K/W
CONDITIONS
V
G2-S
= V
DS
= 0; I
G1-S
= 10 mA
V
G1-S
= V
DS
= 0; I
G2-S
= 10 mA
V
G2-S
= V
DS
= 0; I
S-G1
= 10 mA
V
G1-S
= V
DS
= 0; I
S-G2
= 10 mA
V
G2-S
= 4 V; V
DS
= 5 V; I
D
= 20
µA
V
G1-S
= V
DS
= 5 V; I
D
= 20
µA
V
G2-S
= 4 V; V
DS
= 5 V;
R
G1
= 120 kΩ; note 1
V
G2-S
= V
DS
= 0; V
G1-S
= 5 V
V
G1-S
= V
DS
= 0; V
G2-S
= 5 V
MIN.
6
6
0.5
0.5
0.3
0.3
8
−
−
MAX.
15
15
1.5
1.5
1
1.2
13
50
50
UNIT
V
V
V
V
V
V
mA
nA
nA
DYNAMIC CHARACTERISTICS
Common source; T
amb
= 25
°C;
V
DS
= 5 V; V
G2-S
= 4 V; I
D
= 10 mA; unless otherwise specified.
SYMBOL
y
fs
C
ig1-s
C
ig2-s
C
os
C
rs
F
PARAMETER
forward transfer admittance
input capacitance at gate 1
input capacitance at gate 2
drain-source capacitance
noise figure
f = 1 MHz
f = 1 MHz
f = 1 MHz
f = 200 MHz; G
S
= 2 mS; B
S
= B
Sopt
f = 800 MHz; G
S
= G
Sopt
; B
S
= B
Sopt
CONDITIONS
pulsed; T
j
= 25
°C
MIN.
22
−
1
1
−
−
−
TYP.
25
2.2
1.5
1.4
25
1
2
MAX.
30
2.6
2
1.7
35
1.5
2.8
UNIT
mS
pF
pF
pF
fF
dB
dB
reverse transfer capacitance f = 1 MHz
1999 May 14
4
Philips Semiconductors
Product specification
N-channel dual gate MOS-FETs
BF904A; BF904AR; BF904AWR
40
Y fs
(mS)
30
MLD268
MRA769
0
handbook, halfpage
gain
reduction
(dB)
10
20
20
30
10
40
50
0
50
0
50
100
150
o
T j ( C)
0
1
2
3
VAGC (V)
4
f = 50 MHz.
Fig.5
Transfer admittance as a function of the
junction temperature; typical values.
Fig.6
Typical gain reduction as a function of
the AGC voltage; see Fig.21.
handbook, halfpage
120
MRA771
MLD270
20
ID
(mA)
15
2V
V G2 S = 4 V
3V
2.5 V
Vunw
(dB
µ
V)
110
100
10
1.5 V
90
5
1V
80
0
10
20
30
40
50
gain reduction (dB)
0
0
0.4
0.8
1.2
1.6
2.0
V G1 S (V)
V
DS
= 5 V; V
GG
= 5 V; f
w
= 50 MHz.
f
unw
= 60 MHz; T
amb
= 25
°C;
R
G1
= 120 kΩ.
Fig.7
Unwanted voltage for 1% cross-modulation
as a function of gain reduction; typical
values; see Fig.21.
V
DS
= 5 V.
T
j
= 25
°C.
Fig.8 Transfer characteristics; typical values.
1999 May 14
5
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