INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT670
4 x 4 register file; 3-state
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
Product specification
4 x 4 register file; 3-state
FEATURES
•
Simultaneous and independent read and write
operations
•
Expandable to almost any word size and bit length
•
Output capability: bus driver
•
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT670 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT670 are 16-bit 3-state register files
organized as 4 words of 4 bits each. Separated read and
write address inputs (R
A
, R
B
and W
A
, W
B
) and enable
inputs (RE and WE) are available, permitting simultaneous
writing into one word location and reading from another
location. The 4-bit word to be stored is presented to four
data inputs (D
0
to D
3
). The W
A
and W
B
inputs determine
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
74HC/HCT670
the location of the stored word. When the WE input is
LOW, the data is entered into the addressed location. The
addressed location remains transparent to the data while
the WE input is LOW. Data supplied at the inputs will be
read out in true (non-inverting) form from the 3-state
outputs (Q
0
to Q
3
). D
n
and W
n
inputs are inhibited when
WE is HIGH.
Direct acquisition of data stored in any of the four registers
is made possible by individual read address inputs
(R
A
and R
B
). The addressed word appears at the four
outputs when the RE is LOW. Data outputs are in the high
impedance OFF-state when RE is HIGH. This permits
outputs to be tied together to increase the word capacity to
very large numbers.
Design of the read enable signals for the stacked devices
must ensure that there is no overlap in the LOW levels
which would cause more than one output to be active at
the same time. Parallel expansion to generate n-bit words
is accomplished by driving the enable and address inputs
of each device in parallel.
TYPICAL
SYMBOL PARAMETER
t
PHL
/ t
PLH
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
)
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
;
for HCT the condition is V
I
= GND to V
CC
−1.5
V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
where:
propagation delay D
n
to Q
n
input capacitance
power dissipation capacitance per package
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
23
3.5
122
HCT
23
3.5
124
ns
pF
pF
UNIT
December 1990
2
Philips Semiconductors
Product specification
4 x 4 register file; 3-state
PIN DESCRIPTION
PIN NO.
5, 4
8
10, 9, 7, 6
11
12
14, 13
15, 1, 2, 3
16
SYMBOL
R
A
, R
B
GND
Q
0
to Q
3
RE
WE
W
A
, W
B
D
0
to D
3
V
CC
NAME AND FUNCTION
read address inputs
ground (0 V)
data outputs
3-state output read enable input (active LOW)
write enable input (active LOW)
write address inputs
data inputs
positive supply voltage
74HC/HCT670
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
Fig.4 Functional diagram.
WRITE MODE SELECT TABLE
OPERATING
MODE
write data
data latched
Note
1. The write address (W
A
and W
B
) to the
“internal latches” must be stable while WE is
LOW for conventional operation.
INPUTS
WE
L
L
H
D
n
L
H
X
INTERNAL
LATCHES
(1)
L
H
no change
READ MODE SELECT TABLE
OPERATING
MODE
read
disabled
Notes
1. The selection of the “internal latches” by read address
(R
A
and R
B
) are not constrained by WE or RE operation.
H = HIGH voltage level
L = LOW voltage level
X = don’t care
Z = high impedance OFF-state
3
INPUTS
RE
L
L
H
INTERNAL LATCHES
(1)
L
H
X
OUTPUT
Q
n
L
H
Z
December 1990
Philips Semiconductors
Product specification
4 x 4 register file; 3-state
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
T
amb
(°C)
74HC
SYMBOL
PARAMETER
+25
−40
to
+85
−40
to+125
max.
295
59
50
375
75
64
375
75
64
225
45
38
225
45
38
90
18
15
120
24
20
90
18
15
90
18
15
5
5
5
5
5
5
150
30
26
ns
74HC/HCT670
TEST CONDITIONS
UNIT V
CC
WAVEFORMS
(V)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Fig.6
min. typ. max. min. max. min.
t
PHL
/ t
PLH
propagation delay
R
A
, R
B
to Q
n
propagation delay
WE to Q
n
propagation delay
D
n
to Q
n
3-state output enable time
RE to Q
n
3-state output disable time
RE to Q
n
output transition time
58
21
17
77
28
22
74
27
22
39
14
11
47
17
14
14
5
4
80
16
14
60
12
10
60
12
10
5
5
5
5
5
5
100
20
17
14
5
4
3
1
1
6
2
2
0
0
0
0
0
0
28
10
8
5
195
39
33
250
50
43
250
50
43
150
30
26
150
30
26
60
12
10
100
20
17
75
15
13
75
15
13
5
5
5
5
5
5
125
25
21
245
49
42
315
63
54
315
63
54
190
38
33
190
38
33
75
15
13
t
PHL
/ t
PLH
ns
Fig.7
t
PHL
/ t
PLH
ns
Fig.7
t
PZH
/ t
PZL
ns
Fig.9
t
PHZ
/ t
PLZ
ns
Fig.9
t
THL
/ t
TLH
ns
Fig.6
t
W
write enable pulse width
LOW
set-up time
D
n
to WE
set-up time
W
A
, W
B
to WE
hold time
D
n
to WE
hold time
W
A
, W
B
to WE
latch time
WE to R
A
, R
B
ns
Fig.8
t
su
ns
Fig.8
t
su
ns
Fig.8
t
h
ns
Fig.8
t
h
ns
Fig.8
t
latch
ns
Fig.8
December 1990
NXP MCU
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