SAA7128H; SAA7129H
Digital video encoder
Rev. 03 — 9 December 2004
Product data sheet
1. General description
The SAA7128H; SAA7129H encodes digital C
R
-Y-C
B
video data to an NTSC, PAL or
SECAM CVBS or S-video signal. Simultaneously, RGB or bypassed but interpolated
C
R
-Y-C
B
signals are available via three additional DACs. The circuit at a 54 MHz
multiplexed digital D1 input port accepts two
ITU-R BT.656
compatible C
R
-Y-C
B
data
streams with 720 active pixels per line in 4 : 2 : 2 multiplexed formats, for example MPEG
decoded data with overlay and MPEG decoded data without overlay, where one data
stream is latched at the rising clock edge and the other at the falling clock edge.
It includes a sync/clock generator and on-chip DACs.
2. Features
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
Monolithic CMOS 3.3 V device, 5 V I
2
C-bus optional
Digital PAL/NTSC/SECAM encoder
System pixel frequency 13.5 MHz
54 MHz double-speed multiplexed D1 interface capable of splitting data into two
separate channels (encoded and baseband)
Three Digital-to-Analog Converters (DACs) for CVBS (CSYNC), VBS (CVBS) and C
(CVBS) two times oversampled with 10-bit resolution (signals in brackets optional)
Three DACs for RED (C
R
), GREEN (Y) and BLUE (C
B
) two times oversampled with
9-bit resolution (signals in brackets optional)
An advanced composite sync is available on the CVBS output for RGB display
centering
Real-time control of subcarrier
Cross-color reduction filter
Closed captioning encoding and World Standard Teletext (WST) and North-American
Broadcast Text System (NABTS) teletext encoding including sequencer and filter
Copy Generation Management System (CGMS) encoding (CGMS described by
standard CPR-1204 of EIAJ); 20 bits in lines 20/283 (NTSC) can be loaded via I
2
C-bus
Fast I
2
C-bus control port (400 kHz)
Line 23 Wide Screen Signalling (WSS) encoding
Video Programming System (VPS) data encoding in line 16 (50/625 lines counting)
Encoder can be master or slave
Programmable horizontal and vertical input synchronization phase
Programmable horizontal sync output phase
Internal Color Bar Generator (CBG)
Philips Semiconductors
SAA7128H; SAA7129H
Digital video encoder
s
Macrovision
®
Pay-per-View copy protection system rev. 7.01 and rev. 6.1 optional; this
applies to SAA7128H only. The device is protected by US patents 4631603, 4577216
and 4819098 and other intellectual property rights; use of the Macrovision anti-copy
process in the device is licensed for non-commercial home use only. Reverse
engineering or disassembly is prohibited; please contact your nearest Philips
Semiconductors sales office for more information.
s
Controlled rise/fall times of output syncs and blanking
s
On-chip crystal oscillator (3rd-harmonic or fundamental crystal)
s
Down mode (low output voltage) or power-save mode of DACs
s
QFP44 package
3. Quick reference data
Table 1:
Quick reference data
V
DDD
= 3.0 V to 3.6 V; T
amb
= 0
°
C to 70
°
C; unless otherwise specified.
Symbol
V
DDA
V
DDD
I
DDA
I
DDD
V
i
V
o(p-p)
Parameter
analog supply voltage
digital supply voltage
analog supply current
digital supply current
input signal voltage levels
analog output signal voltages Y,
C and CVBS without load
(peak-to-peak value)
load resistance
low frequency integral linearity
error
low frequency differential linearity
error
ambient temperature
V
DDD
= 3.3 V
[1]
[1]
Conditions
Min
3.15
3.0
-
-
1.25
Typ
3.3
3.3
130
75
1.35
Max
3.45
3.6
150
100
1.50
Unit
V
V
mA
mA
V
TTL compatible
R
L
LE
lf(i)
LE
lf(d)
T
amb
[1]
75
-
-
0
-
-
-
-
300
±3
±1
70
Ω
LSB
LSB
°C
At maximum supply voltage with highly active input signals.
4. Ordering information
Table 2:
Type
number
SAA7128H
SAA7129H
Ordering information
Package
Name
QFP44
Description
plastic quad flat package; 44 leads (lead length 1.3 mm);
body 10
×
10
×
1.75 mm
Version
SOT307-2
9397 750 14325
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 9 December 2004
2 of 55
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Product data sheet
Rev. 03 — 9 December 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14325
5. Block diagram
Philips Semiconductors
V
DDA1
RESET_N SDA
40
V
DD(I2C)
SA
20
21
I
2
C-BUS
INTERFACE
42
SCL
41
XTALI XTALO RCV1 RCV2 TTXRQ XCLK
35
34
7
8
43
37
LLC1
4
V
DDA3
V
DDA4
V
DDA2
25
28
31
36
SAA7128H
SAA7129H
clock and timing
I
2
C-bus control
SYNC/CLOCK
I
2
C-bus control
I
2
C-bus control
I
2
C-bus control
MP7 to MP0
9 to 16 MPpos
SWITCH
MPA
MP
FADER
Y
ENCODER
CB-CR
Y
OUTPUT
INTERFACE
30
D
27
A
24
22
CVBS
(CSYNC)
VBS
(CVBS)
C
(CVBS)
V
SSA1
V
SSA2
V
SSA3
RED
MPneg
MPB
C
VP
I
2
C-bus control
TTX
44
I
2
C-bus
control
Y
I
2
C-bus control
32
33
23
26
A
29
D
RGB
PROCESSOR
SAA7128H; SAA7129H
GREEN
BLUE
CB-CR
5
18
38
6
17
39
2
3
19
mhb572
V
SSD1
V
SSD2
V
SSD3
V
DDD1
V
DDD2
V
DDD3
SP
AP
RTCI
Fig 1. Block diagram
Digital video encoder
3 of 55
Philips Semiconductors
SAA7128H; SAA7129H
Digital video encoder
6. Pinning information
6.1 Pinning
40 RESET_N
43 TTXRQ
RES
SP
AP
LLC1
V
SSD1
V
DDD1
RCV1
RCV2
MP7
1
2
3
4
5
6
7
8
9
34 XTALO
33 V
SSA3
32 V
SSA2
31 V
DDA3
30 CVBS
29 BLUE
28 V
DDA2
27 VBS
26 GREEN
25 V
DDA1
24 C
23 RED
V
SSA1
22
001aac194
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
39 V
DDD3
38 V
SSD3
36 V
DDA4
V
DD(I2C)
20
SAA7128H
SAA7129H
MP6 10
MP5 11
MP4 12
MP3 13
MP2 14
MP1 15
MP0 16
V
DDD2
17
V
SSD2
18
RTCI 19
SA 21
Fig 2. Pin configuration
6.2 Pin description
Table 3:
Symbol
RES
SP
AP
LLC1
V
SSD1
V
DDD1
RCV1
RCV2
Pinning
Pin
1
2
3
4
5
6
7
8
Type
-
I
I
I
supply
supply
I/O
I/O
Description
reserved pin; do not connect
test pin; connected to digital ground for normal operation
test pin; connected to digital ground for normal operation
line-locked clock input; this is the 27 MHz master clock
digital ground 1
digital supply voltage 1
raster control 1 for video port; this pin receives/provides a VS/FS/FSEQ signal
raster control 2 for video port; this pin provides an HS pulse of programmable length or
receives an HS pulse
9397 750 14325
Product data sheet
Rev. 03 — 9 December 2004
35 XTALI
37 XCLK
42 SDA
41 SCL
44 TTX
4 of 55
Philips Semiconductors
SAA7128H; SAA7129H
Digital video encoder
Table 3:
Symbol
MP7
MP6
MP5
MP4
MP3
MP2
MP1
MP0
V
DDD2
V
SSD2
RTCI
Pinning
…continued
Pin
9
10
11
12
13
14
15
16
17
18
19
Type
I
I
I
I
I
I
I
I
supply
supply
I
digital supply voltage 2
digital ground 2
real-time control input; if the LLC1 clock is provided by an SAA7113 or SAA7118, RTCI
should be connected to the RTCO pin of the respective decoder to improve the signal
quality
sense input for I
2
C-bus voltage; connect to I
2
C-bus supply
select I
2
C-bus address; LOW selects slave address 88h, HIGH selects slave address
8Ch
analog ground 1 for RED (C
R
), C (CVBS) and GREEN (Y) outputs
analog output of RED (C
R
) signal
analog output of chrominance (CVBS) signal
analog supply voltage 1 for RED (C
R
) and C (CVBS) outputs
analog output of GREEN (Y) signal
analog output of VBS (CVBS) signal
analog supply voltage 2 for VBS (CVBS) and GREEN (Y) outputs
analog output of BLUE (C
B
) signal
analog output of CVBS (CSYNC) signal
analog supply voltage 3 for BLUE (C
B
) and CVBS (CSYNC) outputs
analog ground 2 for VBS (CVBS), BLUE (C
B
) and CVBS (CSYNC) outputs
analog ground 3 for the DAC reference ladder and the oscillator
crystal oscillator output
crystal oscillator input; if the oscillator is not used, this pin should be connected to
ground
analog supply voltage 4 for the DAC reference ladder and the oscillator
clock output of the crystal oscillator
digital ground 3
digital supply voltage 3
Reset input, active LOW. After reset is applied, all digital I/Os are in input mode; PAL
black burst on CVBS, VBS and C; RGB outputs set to lowest voltage. The I
2
C-bus
receiver waits for the START condition.
serial clock input (I
2
C-bus) with inactive output path
serial data input/output (I
2
C-bus)
teletext request output, indicating when text bits are requested
teletext bit stream input
Description
double-speed 54 MHz MPEG port; it is an input for
ITU-R BT.656
style multiplexed
C
R
-Y-C
B
data; data is sampled on the rising and falling clock edge; data sampled on the
rising edge is then sent to the encoding part of the device; data sampled on the falling
edge is sent to the RGB part of the device (or vice versa, depending on programming)
V
DD(I2C)
SA
V
SSA1
RED
C
V
DDA1
GREEN
VBS
V
DDA2
BLUE
CVBS
V
DDA3
V
SSA2
V
SSA3
XTALO
XTALI
V
DDA4
XCLK
V
SSD3
V
DDD3
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
supply
I
supply
O
O
supply
O
O
supply
O
O
supply
supply
supply
O
I
supply
O
supply
supply
I
RESET_N 40
SCL
SDA
TTXRQ
TTX
41
42
43
44
I/(O)
I/O
O
I
9397 750 14325
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 9 December 2004
5 of 55
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