Data Sheet No. PD94262
IRU3055
5-BIT PROGRAMMABLE 3-PHASE
SYNCHRONOUS BUCK CONTROLLER IC
PRELIMINARY DATA SHEET TEST SPEC
FEATURES
Meets VRM 9.0 Specification
3-Phase Controller with On-Board MOSFET Driver
On-Board DAC programs the output voltage from
1.075V to 1.850V
Loss-less Short Circuit Protection
Programmable Frequency
Synchronous operation allows maximum efficiency
Minimum Part Count
Soft-Start
Power Good Function
Hiccup Mode Current Limit
DESCRIPTION
The IRU3055 is a 3-phase synchronous Buck controller
which provides high performance DC to DC converter for
high current applications.
The IRU3055 controller IC is specifically designed to meet
Intel and AMD specifications for the new microproces-
sor requiring low voltage and high current.
The IRU3055 features under-voltage lockout for both 5V
and 12V supplies, an external and programmable soft-
start function as well as programming the oscillator fre-
quency by using an external resistor.
APPLICATIONS
Intel Pentium 4 and AMD K7
TYPICAL APPLICATION
C1
1uF
D1
C2
0.1uF
Q1
IRF3704S
C3
1uF
L1
1uH
C4
1000uF
12V
V
CH3
V
CH12
5V
C5
1uF
Vcc
V
CL1
V
CL23
HDrv1
R1
OCSet
2.2K
C6
6x 1500uF
L2
Ref
LDrv1
Rt
PGnd1/
OCGnd
CS1
SS
C9
1uF
R3
47K
C10
0.1uF
D4
PGnd2
D3
CS2
D2
HDrv3
D1
D0
C12
22nF
R6
Comp
27K
CS3
Fb
LDrv3
PGnd3
HDrv2
Q2
IRF3711S
1uH
R2
1.5K
C8
1uF
1.5V / 60A
IRU3055
LDrv2
Q3
IRF3704S
Q4
IRF3711S
L3
1uH
R4
1.5K
C11
1uF
Q5
IRF3704S
Q6
IRF3711S
L4
1uH
R5
1.5K
C13
1uF
C14
8x 2700uF
C7
100pF
(Optional)
Figure 1 - Typical application of IRU3055.
PACKAGE ORDER INFORMATION
T
A
(8C)
0 To 70
Rev. 1.4
08/13/02
DEVICE
IRU3055CQ
PACKAGE
36-Pin Plastic QSOP WB (Q)
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1
IRU3055
ABSOLUTE MAXIMUM RATINGS
V
CH12
and V
CH3
Supply Voltage ................................... 30V (not rated for inductor load)
V
CL1
and V
CL23
Supply Voltage ................................... 20V
V
CC
Supply Voltage .................................................. 7V
Storage Temperature Range ...................................... -65°C To 150°C
Operating Junction Temperature Range .....................
0°C To 125°C
PACKAGE INFORMATION
36-PIN WIDE BODY PLASTIC QSOP (Q)
Rt
1
36 V
CL1
35 LDrv1
34 PGnd1
33 OCGnd
32 HDrv1
31 V
CH12
30 HDrv2
29 NC
28 Gnd
27 PGnd2
26 LDrv2
25 V
CL23
24 LDrv3
23 PGnd3
22 HDrv3
21 V
CH3
20 Ref
19 PGood
Comp 2
Fb 3
SS
CS1
CS2
CS3
4
5
6
7
Vcc 8
V
SET
9
D0 10
D1 11
D2 12
D3 13
D4 14
Fault 15
OCSet 16
Gnd 17
SD 18
u
JA
=608C/W
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over V
CL1
=V
CL23
=V
CH12
=V
CH3
=12V, Vcc=5V and T =0 to
A
70°C. Typical values refer to T
A
=25°C. Low duty cycle pulse testing is used which keeps junction and case tem-
peratures equal to the ambient temperature.
PARAMETER
Supply Current Section
Operating Supply Current
SYM
TEST CONDITION
C
L
High Side=3000pF
C
L
Low Side=6000pF
V5
V12 (150KHz frequency)
MIN
TYP
MAX
UNITS
I
CC
I
CLH
VID Section
DAC Output Voltage (Note 1)
DAC Output Line Regulation
DAC Output Temp Variation
VID Input LO
VID Input HI
VID Input Internal Pull-Up
Resistor to 3.3V
V
DAC
L
REG
T
REG
17
30
-1.5
-0.7
19
50
Vs
-0.06
1.4
21
70
+1.5
+0.7
2
0.4
20.4
mA
%
%
%
V
V
KV
4.5 < Vcc < 5.5V
08C < temp < 708C
VID
R
2
12.4
16.4
2
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Rev. 1.4
08/13/02
IRU3055
PARAMETER
SYM
Power Good Section
Under-Voltage Lower Trip Point
PG
UVL
Under-Voltage Upper Trip Point
PG
UVH
UV Hysteresis
PG
HYST
Over-Voltage Upper Trip Point
OV
L
Over-Voltage Lower Trip Point
OV
H
OV Hysteresis
OV
HYST
Power Good Output LO
PG
L
Power Good Output HI
PG
H
UVLO Threshold - 5V
UVLO
5UP
UVLO Hysteresis - 5V
UVLO
5HYST
UVLO Threshold - 12V
UVLO
12UP
UVLO Hysteresis - 12V
UVLO
12HYST
Over-Voltage Section
OVP Threshold
OVP
TH
Error Amp Section
Transconductance
g
m
Input Bias Current
IB
ERR
Input Offset Voltage
VOS
ERR
Current Sense Section
Input Bias Current
IB
CS
Input Offset Voltage
VOS
CS
CS Matching
CS
MATCH
Current Limit Section
OC Threshold Set Current
IB
OC
OC Comp Offset Voltage
VOS
OC
Hiccup Duty Cycle
H
IC
Soft-Start Section
Charge Current
I
SS
Output Drivers Section
Rise Time
TR
L
TR
H
Fall Time
TF
L
TF
H
Dead Band
DB
LH
DB
HL
Oscillator Section
Osc Frequency per Phase
PWM Ramping Voltage
Duty cycle Matching
TEST CONDITION
V
OUT
Ramping Down
V
OUT
Ramping Up
V
OUT
Ramping Up
V
OUT
Ramping Down
R
L
=3mA
R
L
=5K Pull-Up to 5V
Supply Ramping Up
Supply Ramping Down
Supply Ramping Up
Supply Ramping Down
Fault Pin
MIN
0.88Vs
0.89Vs
0.001Vs
1.10Vs
1.09Vs
0.001Vs
0
4.8
4.2
0.22
10.2
0.5
1.1Vs
TYP
0.90Vs
0.91Vs
0.01Vs
1.11Vs
1.10Vs
0.01Vs
0.04
4.9
4.34
0.32
10.5
0.7
1.15Vs
720
2.5
3
0.9
2
2
120
-8
1
7
25
25
160
-3
2.4
10
50
50
130
MAX
0.92Vs
0.93Vs
0.02Vs
1.12Vs
1.11Vs
0.02Vs
0.4
5
4.5
0.42
10.8
0.9
1.2Vs
UNITS
V
V
V
V
V
V
V
V
V
V
V
V
V
mmho
mA
mV
mA
mV
mV
mA
mV
%
mA
ns
ns
ns
CS1, CS2, CS3
Fb to V
SET
CS1, CS2, CS3
CS1 to CS2, CS1 to CS3
Difference between any CS
OCSet @ 0V
OCSet @ OC Threshold
Css=0.1uF
Soft-Start @ 0V
C
L
High Side=3000pF,
C
L
Low Side=6000pF
C
L
High Side=3000pF,
C
L
Low Side=6000pF
C
L
High Side=3000pF,
C
L
Low Side=6000pF,
(Both Measured @ 10%)
0.5
5
6
4
4
200
+2
13
75
75
f
OSC
Rt = 50KV
V
OSC
Peak to Peak
OSC
MATCH
LDrv or HDrv
100
1.98
150
2.02
0.03
200
2.06
KHz
V
%
Note 1:
Vs refers to the set point voltage given in Table 1
Rev. 1.4
08/13/02
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3
IRU3055
D4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
D2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
D1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Vs
1.075
1.100
1.125
1.150
1.175
1.200
1.225
1.250
1.275
1.300
1.325
1.350
1.375
1.400
1.425
1.450
D4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
D2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
D1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Vs
1.475
1.500
1.525
1.550
1.575
1.600
1.625
1.650
1.675
1.700
1.725
1.750
1.475
1.800
1.825
1.850
Table 1 - Set point voltage (Vs) vs. VID codes.
PIN DESCRIPTIONS
PIN#
1
2
3
4
PIN SYMBOL
Rt
Comp
Fb
SS
PIN DESCRIPTION
This pin programs the oscillator frequency in the range of 50KHz to 500KHz with an
external resistor connected from this pin to the ground.
Compensation for error amplifier.
This pin is connected directly to the output of the Core supply to provide feedback to the
Error amplifier.
This pin provides the soft-start for the switching regulator. An internal current source
charges an external capacitor that is connected from this pin to the ground which ramps
up the outputs of the switching regulator, preventing the outputs from overshooting as
well as limiting the input current. The second function of the Soft-Start cap is to provide
long off time (HICCUP) for the synchronous MOSFET during current limiting.
Current sense feedback for channel 1, 2, 3.
5
6
7
8
9
10
CS1
CS2
CS3
Vcc
V
SET
D0
11
D1
12
D2
13
D3
14
D4
5V supply voltage.
Output of the DAC.
LSB input to the DAC that programs the output voltage. This pin is internally connected
to 3.3V by a 16K resistor. This pin can be pulled up externally by a 10K resistor to 5V
supply. This pin programs the output voltage in 25mV steps based on the VID table.
Input to the DAC that programs the output voltage. This pin is internally connected to
3.3V by a 16K resistor. This pin can be pulled up externally by a 10K resistor to 5V
supply.
Input to the DAC that programs the output voltage. This pin is internally connected to
3.3V by a 16K resistor. This pin can be pulled up externally by a 10K resistor to 5V
supply.
Input to the DAC that programs the output voltage. This pin is internally connected to
3.3V by a 16K resistor. This pin can be pulled up externally by a 10K resistor to 5V
supply.
MSB input to the DAC that programs the output voltage. This pin is internally connected
to 3.3V by a 16K resistor. This pin can be pulled up externally by a 10K resistor to 5V
supply.
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Rev. 1.4
08/13/02
4
IRU3055
PIN#
15
16
PIN SYMBOL
Fault
OCSet
PIN DESCRIPTION
Fault detector. When the output exceeds the OVP trip point, the fault pin switches to
2.8V and pulls down the soft-start.
This pin is connected to the drain of the synchronous MOSFET in channel 1 of the Core
supply and it provides the positive sensing for the internal current sensing circuitry. An
external resistor programs the over current threshold depending on the R
DS(ON)
of the
power MOSFET.
Analog ground for internal reference and control circuitry. Connect to PGnd with a short
trace.
Shut down pin. Pulling-up this pin disables the outputs.
Power good pin. This pin is a collector output that switches Low when the output of the
converter is not within
610%(typ)
of the nominal output voltage.
2V reference output.
These pins power the high side MOSFET driver. A minmum 1mF ceramic cap must be
connected from these pins to ground to provide peak drive current capability.
Output drivers for the high side power MOSFET.
17
28
18
19
20
21
31
22
30
32
23
27
34
24
26
35
25
36
Gnd
SD
PGood
Ref
V
CH3
V
CH12
HDrv3
HDrv2
HDrv1
PGnd3
PGnd2
PGnd1
LDrv3
LDrv2
LDrv1
V
CL23
V
CL1
These pins serve as the ground pins and must be connected directly to the ground plane.
A high frequency capacitor (0.1 to 1mF) must be connected from pins V
CL1
, V
CL23
and
V
CH3
, V
CH12
to PGnd1, 2 and 3 for noise free operation.
Output driver for the synchronous power MOSFET.
29
33
NC
OCGnd
These pins are connected to the 12V supply and serves as the power Vcc pin for the low
side output drivers. A high frequency capacitor (0.1 to 1mF) must be connected directly
from these pins to PGnd1, PGnd2 and PGnd3 pins in order to supply the peak current to
the power MOSFET during the transitions.
No connection.
This pin is connected from the source of the synchronous MOSFET in channal 1 of the
Core supply and it provides the reference point for the internal current sensing circuitry.
Rev. 1.4
08/13/02
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5
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