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74HC4094DB,118

产品描述Shift Register/Latch Single 8-Bit Serial to Serial/Parallel 16-Pin SSOP T/R
产品类别计数器移位寄存器   
文件大小270KB,共19页
制造商Nexperia
官网地址https://www.nexperia.com
标准
下载文档 详细参数 选型对比 全文预览

74HC4094DB,118概述

Shift Register/Latch Single 8-Bit Serial to Serial/Parallel 16-Pin SSOP T/R

74HC4094DB,118规格参数

参数名称属性值
欧盟限制某些有害物质的使用Compliant
ECCN (US)EAR99
Part StatusLTB
HTS8542.39.00.01
Logic FamilyHC
Logic FunctionShift Register/Latch
Operation ModeSerial to Serial/Parallel
Number of Elements per Chip1
Number of Element Inputs1
Number of Count Input Enables0
Number of Selection Inputs per Element0
Number of Element Outputs10
Number of Stages8
Direction TypeUni-Directional
Triggering TypePositive-Edge
Maximum Propagation Delay Time @ Maximum CL (ns)195@2V|39@4.5V|33@6V
Absolute Propagation Delay Time (ns)295
Process TechnologyCMOS
输出类型
Output Type
3-State
Minimum Operating Supply Voltage (V)2
Typical Operating Supply Voltage (V)5
Maximum Operating Supply Voltage (V)6
Maximum Quiescent Current (mA)0.008
Propagation Delay Test Condition (pF)50
Parallel Enable InputNo
Terminal Count OutputNo
Minimum Operating Temperature (°C)-40
Maximum Operating Temperature (°C)125
系列
Packaging
Tape and Reel
Supplier PackageSSOP
Pin Count16
Standard Package NameSOP
MountingSurface Mount
Package Height1.8(Max)
Package Length6.4(Max)
Package Width5.4(Max)
PCB changed16
Lead ShapeGull-wing

文档预览

下载PDF文档
74HC4094; 74HCT4094
8-stage shift-and-store bus register
Rev. 8 — 14 November 2018
Product data sheet
1. General description
The 74HC4094; 74HCT4094 is an 8-bit serial-in/serial or parallel-out shift register with a storage
register and 3-state outputs. Both the shift and storage register have separate clocks. The device
features a serial input (D) and two serial outputs (QS1 and QS2) to enable cascading. Data is
shifted on the LOW-to-HIGH transitions of the CP input. Data is available at QS1 on the LOW-to-
HIGH transitions of the CP input to allow cascading when clock edges are fast. The same data
is available at QS2 on the next HIGH-to-LOW transition of the CP input to allow cascading when
clock edges are slow. The data in the shift register is transferred to the storage register when the
STR input is HIGH. Data in the storage register appears at the outputs whenever the output enable
input (OE) is HIGH. A LOW on OE causes the outputs to assume a high-impedance OFF-state.
Operation of the OE input does not affect the state of the registers. Inputs include clamp diodes.
This enables the use of current limiting resistors to interface inputs to voltages in excess of V
CC
.
2. Features and benefits
Complies with JEDEC standard JESD7A
Input levels:
For 74HC4094: CMOS level
For 74HCT4094: TTL level
Low-power dissipation
ESD protection:
HBM JESD22-A114F exceeds 2 000 V
MM JESD22-A115-A exceeds 200 V
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
3. Applications
Serial-to-parallel data conversion
Remote control holding register
4. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range
74HC4094D
74HCT4094D
74HC4094DB
74HCT4094DB
74HC4094PW
-40 °C to +125 °C
TSSOP16
-40 °C to +125 °C
SSOP16
-40 °C to +125 °C
Name
SO16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic thin shrink small outline package;
16 leads; body width 4.4 mm
Version
SOT109-1
SOT338-1
SOT403-1

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