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74LVT573PW,118: 产品描述IC OCTAL D TRANSP LATCH 20TSSOP; 产品类别逻辑逻辑; 文件大小912KB，共17页; 制造商Nexperia; 官网地址https://www.nexperia.com

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74LVT573PW,118概述

IC OCTAL D TRANSP LATCH 20TSSOP

74LVT573PW,118规格参数

参数名称	属性值
Brand Name	Nexperia
零件包装代码	TSSOP2
包装说明	TSSOP,
针数	20
制造商包装代码	SOT360-1
Reach Compliance Code	compliant
其他特性	BROADSIDE VERSION OF 373
系列	LVT
JESD-30 代码	R-PDSO-G20
JESD-609代码	e4
长度	6.5 mm
负载电容（CL）	50 pF
逻辑集成电路类型	BUS DRIVER
湿度敏感等级	1
位数	8
功能数量	1
端口数量	2
端子数量	20
最高工作温度	85 °C
最低工作温度	-40 °C
输出特性	3-STATE
输出极性	TRUE
封装主体材料	PLASTIC/EPOXY
封装代码	TSSOP
封装形状	RECTANGULAR
封装形式	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）	260
最大电源电流（ICC）	12 mA
传播延迟（tpd）	5.2 ns
认证状态	Not Qualified
座面最大高度	1.1 mm
最大供电电压 (Vsup)	3.6 V
最小供电电压 (Vsup)	2.7 V
标称供电电压 (Vsup)	3.3 V
表面贴装	YES
技术	BICMOS
温度等级	INDUSTRIAL
端子面层	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式	GULL WING
端子节距	0.65 mm
端子位置	DUAL
处于峰值回流温度下的最长时间	30
宽度	4.4 mm
Base Number Matches	1

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74LVT573

3.3 V octal D-type transparent latch; 3-state

Rev. 8 — 22 November 2011

Product data sheet

1. General description

The 74LVT573 is a high-performance BiCMOS product designed for V

operation at

3.3 V. This device is an octal transparent latch coupled to eight 3-state output buffers. The

two sections of the device are controlled independently by Latch Enable (LE) and Output

Enable (OE) control gates. The 74LVT573 has a broadside pinout configuration to

facilitate PC board layout and allow easy interface with microprocessors.

The data on the Dn inputs are transferred to the latch outputs when the Latch Enable (LE)

input is High. The latch remains transparent to the data inputs while LE is High, and stores

the data that is present one setup time before the High-to-Low enable transition.

The 3-state output buffers are designed to drive heavily loaded 3-state buses, MOS

memories, or MOS microprocessors. The active-Low Output Enable (OE) controls all

eight 3-state buffers independent of the latch operation.

When OE is Low, the latched or transparent data appears at the outputs. When OE is

High, the outputs are in the High-impedance “OFF” state, which means they will neither

drive nor load the bus.

2. Features and benefits



Inputs and outputs arranged for easy interfacing to microprocessors

3-state outputs for bus interfacing

Common output enable control

TTL input and output switching levels

Input and output interface capability to systems at 5 V supply

Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs

Live insertion and extraction permitted

No bus current loading when output is tied to 5 V bus

Power-up reset

Power-up 3-state

Latch-up protection



JESD78 class II exceeds 500 mA



ESD protection:



HBM JESD22-A114E exceeds 2000 V



MM JESD22-A115-A exceeds 200 V



Specified from

40 C

to +85

C

74LVT573PW,118相似产品对比

	74LVT573PW,118	74LVT573PW,112	74LVT573DB,112	74LVT573PW	74LVT573BQ,115	74LVT573D,118	74LVT573D,112
描述	IC OCTAL D TRANSP LATCH 20TSSOP	74LVT573 - 3.3 V octal D-type transparent latch; 3-state TSSOP2 20-Pin	74LVT573 - 3.3 V octal D-type transparent latch; 3-state SSOP2 20-Pin	Bus Driver	IC OCTAL D TRANSP LATCH 20DHVQFN	IC OCTAL D TRANSP LATCH 20SOIC	IC OCTAL D TRANSP LATCH 20SOIC
包装说明	TSSOP,	TSSOP,	SSOP,	TSSOP-20	HVQCCN,	SOP,	SOP,
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant	compliant
系列	LVT	LVT	LVT	LVT	LVT	LVT	LVT
JESD-30 代码	R-PDSO-G20	R-PDSO-G20	R-PDSO-G20	R-PDSO-G20	R-PQCC-N20	R-PDSO-G20	R-PDSO-G20
JESD-609代码	e4	e4	e4	e4	e4	e4	e4
长度	6.5 mm	6.5 mm	7.2 mm	6.5 mm	4.5 mm	12.8 mm	12.8 mm
逻辑集成电路类型	BUS DRIVER	BUS DRIVER	BUS DRIVER	BUS DRIVER	BUS DRIVER	BUS DRIVER	BUS DRIVER
湿度敏感等级	1	1	1	1	1	1	1
位数	8	8	8	8	8	8	8
功能数量	1	1	1	1	1	1	1
端口数量	2	2	2	2	2	2	2
端子数量	20	20	20	20	20	20	20
最高工作温度	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C
最低工作温度	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
输出特性	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
输出极性	TRUE	TRUE	TRUE	TRUE	TRUE	TRUE	TRUE
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	TSSOP	TSSOP	SSOP	TSSOP	HVQCCN	SOP	SOP
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	SMALL OUTLINE	SMALL OUTLINE
峰值回流温度（摄氏度）	260	260	260	260	260	260	260
传播延迟（tpd）	5.2 ns	5.2 ns	5.2 ns	6.3 ns	5.2 ns	5.2 ns	5.2 ns
座面最大高度	1.1 mm	1.1 mm	2 mm	1.1 mm	1 mm	2.65 mm	2.65 mm
最大供电电压 (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
最小供电电压 (Vsup)	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V
标称供电电压 (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
表面贴装	YES	YES	YES	YES	YES	YES	YES
技术	BICMOS	BICMOS	BICMOS	BICMOS	BICMOS	BICMOS	BICMOS
温度等级	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
端子面层	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold/Silver (Ni/Pd/Au/Ag)	Nickel/Palladium/Gold/Silver (Ni/Pd/Au/Ag)
端子形式	GULL WING	GULL WING	GULL WING	GULL WING	NO LEAD	GULL WING	GULL WING
端子节距	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.5 mm	1.27 mm	1.27 mm
端子位置	DUAL	DUAL	DUAL	DUAL	QUAD	DUAL	DUAL
处于峰值回流温度下的最长时间	30	30	30	30	30	30	30
宽度	4.4 mm	4.4 mm	5.3 mm	4.4 mm	2.5 mm	7.5 mm	7.5 mm
Base Number Matches	1	1	1	1	1	1	1
Brand Name	Nexperia	Nexperia	Nexperia	-	Nexperia	Nexperia	Nexperia
零件包装代码	TSSOP2	TSSOP2	SSOP2	-	QFN	SOP	SOP
针数	20	20	20	-	20	20	20
制造商包装代码	SOT360-1	SOT360-1	SOT339-1	-	SOT764-1	SOT163-1	SOT163-1
其他特性	BROADSIDE VERSION OF 373	BROADSIDE VERSION OF 373	BROADSIDE VERSION OF 373	-	BROADSIDE VERSION OF 373	BROADSIDE VERSION OF 373	BROADSIDE VERSION OF 373
负载电容（CL）	50 pF	50 pF	50 pF	-	-	50 pF	50 pF
最大电源电流（ICC）	12 mA	12 mA	12 mA	-	-	12 mA	12 mA
认证状态	Not Qualified	Not Qualified	Not Qualified	-	Not Qualified	Not Qualified	Not Qualified

74LVT573PW,118

74LVT573PW,118概述

74LVT573PW,118规格参数

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74LVT573PW,118相似产品对比

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