PowerPC is a trademark of IBM, Inc. All other trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS078 (v1.10) June 25, 2007
Product Specification
www.xilinx.com
1
R
Spartan-II/Spartan-IIE Family OTP Configuration PROMs (XC17S00A)
Pin Description
Pins not listed are no connects.
8-pin
PDIP
(PD8/PDG8)
and
VOIC/TSOP
(VO8/VOG8)
1
Pin Name
20-pin
SOIC
(SO20)
1
44-pin
VQFP
(VQ44)
40
Pin Description
DATA
•
Data output, High-Z state when either CE or OE are inactive. During
programming, the DATA pin is I/O. Note that OE can be programmed to
be either active High or active Low.
•
Each rising edge on the CLK input increments the internal address
counter, if both CE and OE are active.
•
When High, this input holds the address counter reset and puts the
DATA output in a high-impedance state. The polarity of this input pin is
programmable as either RESET/OE or OE/RESET. To avoid confusion,
this document describes the pin as RESET/OE, although the opposite
polarity is possible on all devices. When RESET is active, the address
counter is held at zero, and the DATA output is in a high-impedance
state. The polarity of this input is programmable. The default is active-
High RESET, but the preferred option is active Low RESET, because it
can be connected to the FPGAs INIT pin and a pull-up resistor.
•
The polarity of this pin is controlled in the programmer interface. This
input pin is easily inverted using the Xilinx HW-130 programmer software.
Third-party programmers have different methods to invert this pin.
•
When High, this pin resets the internal address counter, puts the DATA
output in a high-impedance state, and forces the device into low-I
CC
standby mode.
•
GND is the ground connection.
•
The V
CC
pins are to be connected to the positive voltage supply.
CLK
RESET/OE
(OE/RESET)
2
3
3
8
43
13
CE
4
10
15
GND
V
CC
5
7, 8
11
18, 20
18, 41
38, 35
Pinout Diagrams
DATA (D0)
CLK
OE/RESET
CE
1
2
3
4
8
PD8/PDG8
7
VO8/VOG8
VCC
VCC
NC
GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
CLK
NC
GND
DATA(D0)
NC
VCC
NC
Top View
5
ds078_04_061805
ds078_05_061805
NC
OE/RESET
NC
CE
NC
NC
GND
NC
NC
NC
NC
DATA(D0)
NC
CLK
NC
NC
NC
NC
OE/RESET
NC
CE
1
2
3
4
SO20
5
Top View
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC
NC
VCC
NC
NC
NC
NC
NC
NC
GND
1
2
3
4
5
6
7
8
9
10
11
44
43
42
41
40
39
38
37
36
35
34
6
VCC
NC
NC
VQ44
Top View
33
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
12
13
14
15
16
17
18
19
20
21
22
ds073_06_061805
DS078 (v1.10) June 25, 2007
Product Specification
www.xilinx.com
2
R
Spartan-II/Spartan-IIE Family OTP Configuration PROMs (XC17S00A)
configuration program from an external memory. The
XC17S00A PROM has been designed for compatibility with
the Master Serial mode.
Upon power-up or reconfiguration, the Spartan device
enters the Master Serial mode when the mode pins are set
to Master Serial mode. Data is read from the PROM
sequentially on a single data line. Synchronization is
provided by the rising edge of the temporary signal CCLK,
which is generated during configuration.
Master Serial mode provides a simple configuration
interface (Figure
1).
Only a serial data line, two control lines,
and a clock line are required to configure the Spartan
device. Data from the PROM is read sequentially, accessed
via the internal address and bit counters which are
incremented on every valid rising edge of CCLK.
If the user-programmable, dual-function D
IN
pin on the
Spartan device is used only for configuration, it must still be
held at a defined level during normal operation. The
Spartan-II/Spartan-IIE family takes care of this
automatically with an on-chip pull-up/down resistor or
keeper circuit.
The one-time-programmable XC17S00A PROM in
Figure 1, page 3
supports automatic loading of
configuration programs. An early DONE inhibits the PROM
data output one CCLK cycle before the Spartan FPGA I/Os
become active.
Controlling PROMs
•
•
•
•
Connecting the Spartan device with the PROM:
The DATA output of the PROM drives the D
IN
input of
the lead Spartan device.
The Master Spartan device CCLK output drives the
CLK input of the PROM.
The RESET/OE input of the PROM is connected to the
INIT pin of the Spartan device and a pull-up resistor.
This connection assures that the PROM address
counter is reset before the start of any
(re)configuration, even when a reconfiguration is
initiated by a V
CC
glitch.
The CE input of the PROM is connected to the DONE
pin of the Spartan device and a pull-up resistor. CE can
also be permanently tied Low, but this keeps the DATA
output active and causes an unnecessary supply
current of 10 mA maximum.
•
FPGA Master Serial Mode Summary
The I/O and logic functions of the Configurable Logic Block
(CLB) and their associated interconnections are established
by a configuration program. The program is loaded either
automatically upon power up, or on command, depending
on the state of the Spartan device mode pins. In Master
Serial mode, the Spartan device automatically loads the
Spartan-II/
Spartan-IIE
Master
Serial
M0
M1
M2
D
IN
CCLK
DONE
INIT
3.3V
3.3
KΩ
3.3V
V
CC
3.3
KΩ
DATA
CLK
CE
V
CC
XC17S00A
PROM
OE/RESET
Notes:
1. If the DriveDone configuration option is not
active,
pull
up
DONE with
a 3.3
kΩ resistor.
DS078_01_061107
Figure 1:
XC17S00A PROM Connections to FPGA in Master Serial Mode
DS078 (v1.10) June 25, 2007
Product Specification
www.xilinx.com
3
R
Spartan-II/Spartan-IIE Family OTP Configuration PROMs (XC17S00A)
Standby Mode
The PROM enters a low-power standby mode whenever CE
is asserted High. The output remains in a high-impedance
state regardless of the state of the OE input.
Programming Spartan-II/Spartan-IIE
Family PROMs
The devices can be programmed on programmers supplied
by Xilinx or qualified third-party vendors. The user must
ensure that the appropriate programming algorithm and the
latest version of the programmer software are used. The
wrong choice can permanently damage the device.
VCC
GND
RESET/
OE
or
OE/
RESET
CE
CLK
Address Counter
TC
EPROM
Cell
Matrix
Output
OE
DATA
DS030_02_011300
Figure 2:
Simplified Block Diagram (does not show programming circuit)
Caution!
Always tie the two V
CC
pins together.
Table 1:
Truth Table for XC17S00A Control Inputs
Control Inputs
RESET
(1)
Inactive
Active
Inactive
Active
Notes:
1.
2.
The XC17S00A RESET input has programmable polarity
微控制器 MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
