0
R
Spartan Family of One-Time
Programmable Configuration
PROMs (XC17S00)
5
DS030 (v1.8) October 10, 2001
0
Product Specification
Introduction
The Spartan
™
family of PROMs provides an easy-to-use,
cost-effective method for storing Spartan device configura-
tion bitstreams.
When the Spartan device is in Master Serial mode, it gener-
ates a configuration clock that drives the Spartan PROM. A
short access time after the rising clock edge, data appears
on the PROM DATA output pin that is connected to the Spar-
tan device D
IN
pin. The Spartan device generates the
appropriate number of clock pulses to complete the config-
uration. Once configured, it disables the PROM. When a
Spartan device is in Slave Serial mode, the PROM and the
Spartan device must both be clocked by an incoming signal.
For device programming, either the Xilinx Alliance or the
Foundation series development systems compiles the Spar-
tan device design file into a standard HEX format which is
then transferred to most commercial PROM programmers.
Spartan PROM Features
•
Configuration one-time programmable (OTP) read-only
memory designed to store configuration bitstreams for
Spartan, Spartan-XL, and Spartan-II FPGA devices
Simple interface to the Spartan device requires only
one user I/O pin
Programmable reset polarity (active High or active
Low)
Low-power CMOS floating gate process
Available in 5V and 3.3V versions
Available in compact plastic 8-pin DIP, 8-pin VOIC, or
20-pin SOIC packages.
Programming support by leading programmer
manufacturers.
Design support using the Xilinx Alliance and
Foundation series software packages.
Guaranteed 20 year life data retention
•
•
•
•
•
•
•
•
Spartan FPGA
XCS05
XCS05XL
XCS10
XCS10XL
XCS20
XCS20XL
XCS30
XCS30XL
XCS40
XCS40XL
XC2S50
XC2S100
XC2S150
Configuration Bits
53,984
54,544
95,008
95,752
178,144
179,160
247,968
249,168
329,312
330,696
559,232
781,248
1,040,128
Compatible Spartan PROM
XC17S05
XC17S05XL
XC17S10
XC17S10XL
XC17S20
XC17S20XL
XC17S30
XC17S30XL
XC17S40
XC17S40XL
XC17S50XL
XC17S100XL
XC17S150XL
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS030 (v1.8) October 10, 2001
Product Specification
www.xilinx.com
1-800-255-7778
1
Spartan Family of One-Time Programmable Configuration PROMs (XC17S00)
R
Pin Description
Table 1:
Spartan PROM Pinouts
8-pin
Pin Name
DATA
PDIP and
VOIC
1
20-pin
SOIC
1
Pin Description
Data output, High-Z state when either CE or OE are inactive. During programming,
the DATA pin is I/O. Note that OE can be programmed to be either active High or
active Low.
Each rising edge on the CLK input increments the internal address counter, if both
CE and OE are active.
When High, this input holds the address counter reset and puts the DATA output in
a high-impedance state. The polarity of this input pin is programmable as either
RESET/OE or OE/RESET. To avoid confusion, this document describes the pin as
RESET/OE, although the opposite polarity is possible on all devices. When RESET
is active, the address counter is held at zero, and the DATA output is in a
high-impedance state. The polarity of this input is programmable. The default is
active High RESET, but the preferred option is active Low RESET, because it can
be driven by the FPGAs INIT pin.
The polarity of this pin is controlled in the programmer interface. This input pin is
easily inverted using the Xilinx HW-130 programmer software. Third-party
programmers have different methods to invert this pin.
CE
GND
V
CC
4
5
7, 8
10
11
18, 20
When High, this pin disables the internal address counter, puts the DATA output in
a high-impedance state, and forces the device into low-I
CC
standby mode.
GND is the ground connection.
The V
CC
pins are to be connected to the positive voltage supply.
CLK
RESET/OE
(OE/RESET)
2
3
3
8
Notes:
1. Pins not listed in the table are reserved and
must
not be externally connected.
Controlling PROMs
Connecting the Spartan device with the PROM:
•
•
•
The DATA output of the PROM drives the D
IN
input of
the lead Spartan device.
The Master Spartan device CCLK output drives the
CLK input of the PROM.
The RESET/OE input of the PROM is driven by the
INIT output of the Spartan device. This connection
assures that the PROM address counter is reset before
the start of any (re)configuration, even when a
reconfiguration is initiated by a V
CC
glitch. Other
methods—such as driving RESET/OE from LDC or
system reset—assume that the PROM internal
power-on-reset is always in step with the FPGAs
internal power-on-reset, which may not be a safe
assumption.
The CE input of the PROM is driven by the DONE
output of the Spartan device, provided that DONE is
not permanently grounded. Otherwise, LDC can be
used to drive CE, but must then be unconditionally
High during user operation. CE can also be
permanently tied Low, but this keeps the DATA output
active and causes an unnecessary supply current of
10 mA maximum.
FPGA Master Serial Mode Summary
The I/O and logic functions of the Configurable Logic Block
(CLB) and their associated interconnections are established
by a configuration program. The program is loaded either
automatically upon power up, or on command, depending
on the state of the Spartan device MODE pin. In Master
Serial mode, the Spartan device automatically loads the
configuration program from an external memory. The Spar-
tan PROM has been designed for compatibility with the
Master Serial mode.
Upon power-up or reconfiguration, the Spartan device
enters the Master Serial mode when the MODE pin is Low.
Data is read from the PROM sequentially on a single data
line. Synchronization is provided by the rising edge of the
temporary signal CCLK, which is generated during configu-
ration.
DS030 (v1.8) October 10, 2001
Product Specification
•
2
www.xilinx.com
1-800-255-7778
R
Spartan Family of One-Time Programmable Configuration PROMs (XC17S00)
unchanged after configuration is complete. Therefore, to
reprogram the FPGA with another program, the DONE line
is pulled Low and configuration begins at the last value of
the address counters.
This method fails if a user applies RESET during the Spar-
tan device configuration process. The Spartan device
aborts the configuration and then restarts a new configura-
tion, as intended, but the PROM does not reset its address
counter, since it never saw a High level on its OE input. The
new configuration, therefore, reads the remaining data in
the PROM and interprets it as preamble, length count etc.
Since the Spartan device is the Master, it issues the neces-
sary number of CCLK pulses, up to 16 million (2
24
) and
DONE goes High. However, the Spartan device configura-
tion will be completely wrong, with potential contentions
inside the Spartan device and on its output pins. This
method must, therefore, never be used when there is any
chance of external reset during configuration.
Master Serial mode provides a simple configuration inter-
face (Figure
1).
Only a serial data line and two control lines
are required to configure the Spartan device. Data from the
PROM is read sequentially, accessed via the internal
address and bit counters which are incremented on every
valid rising edge of CCLK.
If the user-programmable, dual-function D
IN
pin on the
Spartan device is used only for configuration, it must still be
held at a defined level during normal operation. The Spar-
tan family takes care of this automatically with an on-chip
default pull-up resistor.
Programming the FPGA With Counters
Unchanged Upon Completion
When multiple-configurations for a single Spartan device
are stored in a PROM, the OE pin should be tied Low. Upon
power-up, the internal address counters are reset and con-
figuration begins with the first program stored in memory.
Since the OE pin is held Low, the address counters are left
Spartan
Master Serial
MODE
3.3V
V
CC
4.7K
V
CC
V
CC
D
IN
CCLK
DONE
INIT
DATA
CLK
CE
Spartan
PROM
OE/RESET
(Low Resets the Address Pointer)
CCLK
(Output)
D
IN
D
OUT
(Output)
DS030_01_101001
Figure 1:
Master Serial Mode.
The one-time-programmable Spartan PROM supports automatic loading of configuration programs.
An early DONE inhibits the PROM data output one CCLK cycle before the Spartan FPGA I/Os become active.
DS030 (v1.8) October 10, 2001
Product Specification
www.xilinx.com
1-800-255-7778
3
Spartan Family of One-Time Programmable Configuration PROMs (XC17S00)
R
Standby Mode
The PROM enters a low-power standby mode whenever CE
is asserted High. The output remains in a high-impedance
state regardless of the state of the OE input.
Programming the Spartan Family
PROMs
The devices can be programmed on programmers supplied
by Xilinx or qualified third-party vendors. The user must
ensure that the appropriate programming algorithm and the
latest version of the programmer software are used. The
wrong choice can permanently damage the device.
VCC
GND
RESET/
OE
or
OE/
RESET
CE
CLK
Address Counter
TC
EPROM
Cell
Matrix
Output
OE
DATA
DS030_02_011300
Figure 2:
Simplified Block Diagram (does not show programming circuit)
Important:
Á
Always tie the two V
CC
pins together in your application.
Table 2:
Truth Table for XC17S00 Control Inputs
Control Inputs
RESET
(1)
Inactive
Active
Inactive
Active
CE
Low
Low
High
High
Internal Address
(2)
If address < TC: increment
If address > TC: don’t change
Held reset
Not changing
Held reset
DATA
Active
High-Z
High-Z
High-Z
High-Z
Outputs
I
CC
Active
Reduced
Active
Standby
Standby
Notes:
1. The XC17S00 RESET input has programmable polarity
2. TC = Terminal Count = highest address value. TC + 1 = address 0.
4
www.xilinx.com
1-800-255-7778
DS030 (v1.8) October 10, 2001
Product Specification
R
Spartan Family of One-Time Programmable Configuration PROMs (XC17S00)
XC17S05, XC17S10, XC17S20, XC17S30, XC17S40
Absolute Maximum Ratings
(1)
Symbol
V
CC
V
IN
V
TS
T
STG
T
SOL
Description
Supply voltage relative to GND
Input voltage relative to GND
Voltage applied to High-Z output
Storage temperature (ambient)
Maximum soldering temperature (10s @ 1/16 in.)
Value
–0.5 to +7.0
–0.5 to V
CC
+0.5
–0.5 to V
CC
+0.5
–65 to +150
+260
Units
V
V
V
p
C
p
C
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Operating Conditions
(1)
Symbol
V
CC
Description
Commercial
Industrial
Conditions
Supply voltage relative to GND (T
A
= 0
p
C to +70
p
C)
Supply voltage relative to GND (T
A
= –40
p
C to +85
p
C)
Min
4.75
4.50
Max
5.25
5.50
Units
V
V
Notes:
1. During normal read operation both V
CC
pins must be connected together.
DC Characteristics Over Operating Condition
Symbol
V
IH
V
IL
V
OH
V
OL
V
OH
V
OL
I
CCA
I
CCS
High-level input voltage
Low-level input voltage
High-level output voltage (I
OH
= –4 mA)
Low-level output voltage (I
OL
= +4 mA)
High-level output voltage (I
OH
= –4 mA)
Low-level output voltage (I
OL
= +4 mA)
Supply current, active mode (at maximum frequency)
Supply current, standby mode
XC17S05, XC17S10,
XC17S20, XC17S30
XC17S40
I
L
C
IN
C
OUT
Input or output leakage current
Input Capacitance (V
IN
= GND, f = 1.0 MHz)
Output Capacitance (V
IN
= GND, f = 1.0 MHz)
Industrial
Commercial
Description
Min
2.0
0
3.86
-
3.76
-
-
-
-
–10
-
-
Max
V
CC
0.8
-
0.32
-
0.37
10
50
100
10
10
10
Units
V
V
V
V
V
V
mA
N
A
N
A
N
A
pF
pF
DS030 (v1.8) October 10, 2001
Product Specification
www.xilinx.com
1-800-255-7778
5
聊聊、笑笑、闹闹
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
