Si838x Data Sheet
Bipolar Digital Field Inputs for PLCs and Industrial I/O Modules
The Si838x provides eight channels for 24 V digital field interface to either sinking or
sourcing inputs with integrated safety rated isolation. In combination with a few external
components, this provides compliance to IEC 61131-2 switch types 1, 2, or 3. The input
interface is based on Silicon Labs' ground-breaking CMOS based LED emulator technol-
ogy which enables the bipolar capability (sinking or sourcing inputs) with no VDD re-
quired on the field side. The output interface to the controller allows for low power opera-
tion with 2.25 V operation capability. These products utilize Silicon Laboratories' propri-
etary silicon isolation technology, supporting up to 2.5 kV
RMS
withstand voltage. This
technology enables high CMTI (50 kV/μs), lower prop delays and skew, reduced varia-
tion with temperature and age, and tighter part-to-part matching.
Product options include parallel or serialized outputs. Cascading capability for a total of
128 channels (16x Si838x) is possible with serial output option. The Si838x offers longer
service life and dramatically higher reliability compared to opto-coupled input solutions.
Applications:
• Programmable logic controllers
• Industrial data acquisition
• Distributed control systems
• CNC machines
• I/O modules
• Motion control systems
Safety Regulatory Approvals:
• UL 1577 recognized
• Up to 2500 V
RMS
for one minute
• CSA component notice 5A approval
• IEC 60950-1
• VDE certification conformity
• VDE 0884-10
• CQC certification approval
• GB4943.1
KEY FEATURES
• Bipolar digital interface with 24 V sinking or
sourcing inputs
• Eight total inputs in one package
• High data rates of up to 2 Mbps
• Safety rated integrated isolation of 2.5
kVrms
• Low input current of 1 mA typ
• No VDD required on field side
• Status LEDs on parallel outputs
• High electromagnetic immunity
• Programmable debounce times of up to
100 ms
• Transient immunity of 50 kV/μs
• Flow-through output configuration with eight
outputs
• Option for SPI interface serialized outputs
with daisy-chain capability
• Wide 2.25 to 5.5 V VDD operation
• Wide operating temperature range
• –40 to +125 °C
• Compliant to IEC 61131-2
• Type 1, 2, 3
• RoHS-compliant packages
• QSOP-20
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Si838x Data Sheet
Ordering Guide
1. Ordering Guide
Table 1.1. Si838x Ordering Guide
Ordering
Part Number
Si8380P-IU
Si8382P-IU
Si8384P-IU
Si8388P-IU
Si8380S-IU
Si8380PF-IU
Si8382PF-IU
Si8384PF-IU
Si8380PM-IU
Si8382PM-IU
Si8384PM-IU
Si8380PS-IU
Si8382PS-IU
Si8384PS-IU
Serial or Parallel
Output
P
P
P
P
S
P
P
P
P
P
P
P
P
P
Number of High-
Speed Channels
0
2
4
8
0
0
2
4
0
2
4
0
2
4
Low Pass
Filter Delay
0 ms
0 ms
0 ms
0 ms
0 ms
10 ms
10 ms
10 ms
30 ms
30 ms
30 ms
100 ms
100 ms
100 ms
Package Type
Isolation Rating
20-QSOP
20-QSOP
20-QSOP
20-QSOP
20-QSOP
20-QSOP
20-QSOP
20-QSOP
20-QSOP
20-QSOP
20-QSOP
20-QSOP
20-QSOP
20-QSOP
2.5 kVrms
2.5 kVrms
2.5 kVrms
2.5 kVrms
2.5 kVrms
2.5 kVrms
2.5 kVrms
2.5 kVrms
2.5 kVrms
2.5 kVrms
2.5 kVrms
2.5 kVrms
2.5 kVrms
2.5 kVrms
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Si838x Data Sheet
Functional Description
2. Functional Description
2.1 Theory of Operation
The operation of a Si838x channel is analogous to that of a bipolar opto-coupler, except an RF carrier is modulated instead of light. This
simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up. A simplified
block diagram for a single Si838x channel is shown in the figure below.
This product enables 24 V bipolar digital inputs to be connected to its input through a resistor network which acts as a voltage divider.
The inputs can be sourcing or sinking type. To enable this functionality, there is a zero drop bridge and an LED emulator at the front
end that drives an OOK (On-Off Key) modulator/demodulator across the capacitive isolation barrier.
On the output side, the debounce block controls the amount of debounce desired. There are four debounce delay time options availa-
ble: no delay, or delays of 10, 30, or 100 ms. In addition, the user can use the SPI control to program user-specific debounce modes as
explained in Section
2.3.2 Debounce Filtering Modes.
The user-specific debounce programming is only available on the product option
with SPI interface.
A
CMOS isolation barrier
HF
Transmitter
VDD
e
Modulator
Demodulator
Debounce
B
COM
Figure 2.1. Simplified Channel Diagram
2.2 Serial Peripheral Interface
The Si8380S includes a Serial Peripheral Interface (SPI) that provides control and monitoring capability of the isolated channels using a
commonly available microcontroller protocol. The direct-mapped registers allow an external master SPI controller to monitor the status
of the eight PLC channels, as well as to control the delay and filtering modes for the debounce of each channel. Additionally, support is
provided to easily daisy-chain up to sixteen PLC devices. Each of these daisy-chained devices may be uniquely addressed by one
master SPI controller.
2.2.1 SPI Register Map
The addressable SPI registers include one eight-bit register to reflect the status of each of the eight channels, which is read-only. Also,
four additional registers provide two bits to specify the debounce delay, and two bits to specify the debounce filtering mode for each of
the eight channels. These user accessible SPI registers are illustrated in the following table.
Table 2.1. Si838x SPI Register Map
Name
CHAN_STATUS
DBNC_MODE0
DBNC_MODE1
DBNC_DLY0
DBNC_DLY1
Address
0x0
0x1
0x2
0x3
0x4
Access
R
R/W
R/W
R/W
R/W
Description
Current value of each of the eight PLC channels {PLC[7:0]}
Mode control bits for the first four channel debounce filters organized as:
{md_ch3[1:0],md_ch2[1:0],md_ch1[1:0],md_ch0[1:0]}
Mode control bits for the second four channel debounce filters organized as:
{md_ch7[1:0],md_ch6[1:0],md_ch5[1:0],md_ch4[1:0]}
Delay control bits for the first four channel debounce filters organized as:
{dly_ch3[1:0],dly_ch2[1:0],dly_ch1[1:0],dly_ch0[1:0]}
Delay control bits for the second four channel debounce filters organized as:
{dly_ch7[1:0],dly_ch6[1:0],dly_ch5[1:0],dly_ch4[1:0]}
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Si838x Data Sheet
Functional Description
2.2.2 SPI Communication Transactions
SPI communication is performed using a four wire control interface. The four Si838x device pins utilized for SPI include:
• SCLK (input) the SPI clock
• NSS (input) active low device select
• MOSI (input) master-out-slave-in
• MISO (output) master-in-slave-out
Additionally, a fifth wire SDI_THRU (output) is provided as an Si838x device pin to facilitate daisy chaining.
An Si838x SPI communication packet is composed of three serial bytes. In this sequence, byte0 is the control byte, and specifies the
operation to be performed as well as the device to be selected in a daisy chain organization. The CID[3:0] field should be set to all
zeros by the SPI master in non-daisy-chained operation. Next, byte1 specifies the address of the internal Si838x SPI register to be
accessed. The final byte in the packet consists of either the data to be written to the addressed Si838x SPI register (using MOSI), or the
data read from the addressed Si838x SPI register (using MISO). Details of the SPI communication packet are presented in the following
figure for an Si838x SPI write transaction.
NSS
SCLK
MOSI
Control[7:0]
Control Byte
7
6
5
0
4
0
3
2
1
0
R/Wb
2
A[2]
1
A[1]
0
A[0]
CTL[5:4]
CID[3:0]
2
D[2]
1
D[1]
0
D[0]
Address[7:0]
BRCT
Data[7:0]
1 - broadcast (write)
0 - only addressed part (write)
Ignored on reads
1 - read
0 - write
Reserved (set to 0,0)
Daisy-chained part ID (0) is closest to the master
MOSI. Accomplished by decrementing the CID as
it passes through to the next Si838x device in the
daisy chain on SDI_THRU
BRCT R/Wb
CID[0] CID[1] CID[2] CID[3]
Address Byte
7
A[7]
6
A[6]
5
A[5]
4
A[4]
3
A[3]
Data Byte
7
D[7]
6
D[6]
5
D[5]
4
D[4]
3
D[3]
Figure 2.2. SPI Communication Packet Structure, Write Operation and Control Byte Structure
The SPI master will provide the timing of the signals and framing of the communication packets for all Si838x SPI inputs: NSS, SCLK,
and MOSI. Data is communicated from the SPI master to the Si838x using the MOSI signal. The NSS and SCLK signals provide the
necessary control and timing reference allowing the Si838x to discern valid data on the MOSI signal. Data is returned to the SPI master
by the Si838x utilizing the MISO signal only during the final byte of a three byte SPI read communication packet. At all other times, the
MISO signal is tri-stated by the Si838x. Each of the eight bits for these three packets is captured by the Si838x on eight adjacent rising
edges of SCLK. Each frame of eight bits is composed within bounding periods where the device select, NSS, is deasserted. Upon the
reception of the eight bits within a byte transaction, the deassertion of NSS advances the byte counter within the internal Si838x SPI
state machine. Should the transmission of an eight bit packet be corrupted, either with the deassertion of NSS before the eighth rising
edge of SCLK, or with the absence of the deassertion of NSS after the eighth rising edge of SCLK, the internal SPI state machine may
become unsynchronized with the master SPI controller.
To re-establish SPI synchronization with the Si838x, the SPI master may, at any time, deassert the SPI device select signal NSS, and
force a clock cycle on SCLK. When unsynchronized, the rising edge of SCLK when NSS is deasserted (high) re-initializes the internal
SPI state machine. The Si838x will then treat the immediately following eight bit SPI transaction after NSS is once again asserted as
the first byte in a three byte SPI communication packet.
Any preceding communication packet will be abandoned by the Si838x at the point synchronization is lost, and the NSS signal is deas-
serted. This could occur at any point in the three byte sequence of a SPI communication packet. One should note that abandoning a
SPI write operation early, even during the last byte of the three byte SPI communication packet, will leave the destination register un-
changed. However, if the number of SCLK cycles exceeds eight during the last byte of the three byte SPI write packet, the destination
Si838x register may be corrupted. To remedy both of these situations, it is recommended that such a corrupted write operation be re-
peated immediately following resynchronization of the SPI interface.
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Si838x Data Sheet
Functional Description
2.2.3 SPI Read Operation
Referring to
Figure 2.2 SPI Communication Packet Structure, Write Operation and Control Byte Structure on page 3,
in a SPI read op-
eration the control byte will only have bit6 set to a 1 in a single Si838x device organization (no daisy-chaining). For the Si838x, bit7 (the
broadcast bit) is ignored during a read operation since only one device may be read at a time in either a single or daisy chained organi-
zation.
The second byte in the three byte read packet is provided by the SPI master to designate the address of the Si838x internal register to
be queried. If the read address provided does not correspond to a physically available Si838x internal register, all zeroes will be re-
turned as the read value by the Si838x.
The read data is provided during the final byte of the three byte read communication packet to the querying master SPI device utilizing
the Si838x’s MISO output, which remains tristated at all other times.
The SPI read operation timing diagram is illustrated in the figure below.
NSS
SCLK
MOSI
MISO
Figure 2.3. SPI Read Operation
Control[7:0]
Address[7:0]
ReadData[7:0]
2.2.4 SPI Write Operation
Again referring to
Figure 2.2 SPI Communication Packet Structure, Write Operation and Control Byte Structure on page 3,
in a SPI
write operation the control byte may optionally have bit7 (the broadcast bit) set to a 1. During a SPI write operation, the broadcast bit
forces all daisy-chained Si838x devices to update the designated internal SPI register with the supplied write data, regardless of the
Si838x device being addressed using the CID[3:0] field of the control word.
The second byte in the three byte write packet is provided by the SPI master to designate the address of the Si838x internal register to
be updated. If the write address provided does not correspond to a physically available Si838x internal register, no internal Si838x SPI
register update will occur.
The write data is provided by the SPI master during the final byte of the three byte write communication packet. The Si838x MISO
output remains tri-stated during the entire SPI write operation.
The SPI write operation timing diagram is illustrated in the figure below.
NSS
SCLK
MOSI
MISO
Figure 2.4. SPI Write Operation
Control[7:0]
Address[7:0]
WriteData[7:0]
hiZ
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