200Pin DDR2 1.8V 800 SODIMM
1GB Based on 128Mx8
AQD-SD21GN80-SX
Description
AQD-SD21GN80-SX is 128Mx64 bits DDR2 SDRAM
Module, The module is composed of eight 128Mx8 bits
CMOS DDR2 SDRAMs in FBGA package and one 2Kbit
EEPROM in 8pin TSSOP(TSOP) package on a 200pin
glass–epoxy printed circuit board.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible
on both edges of DQS. Range of operation frequencies,
programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
Pin Identification
Symbol
A0~A13, BA0~BA2
DQ0~DQ63
DQS0~DQS7
/DQS0~/DQS7
CK0, /CK0,CK1, /CK1
CKE0, CKE1
ODT0, ODT1
Function
Address/Bank input
Bi-direction data bus.
Data strobes
Differential Data strobes
Clock Input. (Differential pair)
Clock Enable Input.
On-die termination control line
DIMM rank select lines.
Row address strobe
Column address strobe
Write Enable
Data masks/high data strobes
Core power supply
Power Supply reference
SPD EEPROM power supply
I2C serial bus address select for
SA0~SA1
EEPROM
SCL
SDA
VSS
NC
I2C serial bus clock for EEPROM
I2C serial bus data for EEPROM
Ground
No Connection
Features
• Power supply (Normal): VDD & VDDQ = 1.8V ± 0.1V
• 1.8V (SSTL_18 compatible) I/O
• MRS Cycle with address key programs
- CAS Latency (4, 5, 6)
- Burst Length (4,8)
• Programmable Additive Latency: 0,1,2,3,4,5
• Bi-directional, differential data strobe (DQS and /DQS)
• Differential clock input (CK, /CK) operation
• DLL aligns DQ and DQS transition with CK transition
• Double-data-rate architecture
• Auto refresh and self refresh
• Average Refresh period 7.8 us
• Off-Chip Driver (OCD) Impedance Adjustment
• On Die Termination
• Lead-free and Halogen-free products are RoHS
Compliant
/CS0 ,/CS1
/RAS
/CAS
/WE
DM0~DM7
VDD
V
REF
V
DD
SPD
2
微控制器 MCU
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