RM24C32DS
32-Kbit 1.65V Minimum
Non-volatile Serial EEPROM
I
2
C Bus
Advance Datasheet
Features
Memory array: 32-Kbit non-volatile serial EEPROM memory
Single supply voltage: 1.65V - 3.6V
2-wire I
2
C interface
Compatible with I
2
C bus modes:
-100kHz
-400kHz
-1MHz
Page size: 32 bytes
-Byte and Page Write from 1 to 32 bytes
128-byte, One-Time Programmable (OTP) Security Register
- 64 bytes factory programmed with a unique identifier
- 64 bytes user programmable
Low Energy Byte Write
-Byte Write consuming 50 nJ
Low power consumption
-0.25 mA active Read current
-1.0 mA active Write current
-1.0 µA Standby current
Fast Write
-Page Write in 1.5 ms (32 byte page)
-Byte Write within 60 µs
Random and sequential Read modes
Industry’s lowest read cycle latency
Unlimited read cycles
Write protect of the whole memory array
8-lead SOIC, 8-lead TSSOP, 8-pad UDFN and WLCSP packages
RoHS-compliant and halogen-free packaging
Data Retention: >40 years at 125
°
C
Endurance: 100,000 write cycles (for both byte and page write cycles)
- No degradation across temperature range
No data loss under UV exposure on bare die or WLCSP
Based on Adesto's proprietary CBRAM
®
technology
Description
The Adesto® RM24C32DS is a 32Kbit, serial EEPROM device that utilizes Adesto's
CBRAM® resistive memory technology. The memory devices use a single low-voltage
supply ranging from 1.65V to 3.6V.
DS-RM24C32DS–117B–11/2016
The Adesto
®
I
2
C device is accessed through a 2-wire I
2
C compatible interface consisting of a Serial Data (SDA) and
Serial Clock (SCL). The maximum clock (SCL) frequency is 1MHz. The devices have both byte write and page write
capability. Page write is 32 bytes. The Byte Write operation of CBRAM consumes only 10% of the energy consumed by
a Byte Write operation of EEPROM devices of similar size.
Adesto's EEPROM endurance can be as much as 40X higher than industry standard EEPROM devices operating in byte
write mode at 85°C. Unlike EEPROMs based on floating gate technology (which require read-modify-write on a whole
page for every write operation) CBRAM write endurance is based on the capability to write each byte individually,
irrespective of whether the user writes single bytes or an entire page. Additionally, unlike floating gate technology,
CBRAM does not experience any degradation of endurance across the full temperature range. By contrast, in order to
modify a single byte, most EEPROMs modify and write full pages of 32, 64 or 128 bytes. This provides significantly less
endurance for floating gate devices used in byte write mode when compared to page write mode.
The Page Write operation of CBRAM is 4-6 times faster than the Page Write operation of similar EEPROM devices. Both
random and sequential reads are available. Sequential reads are capable of reading the entire memory in one operation.
External address pins permit up to eight devices on the same data bus. The devices are available in standard 8-pin
SOIC, TSSOP and 8-pad UDFN.
RM24C32DS
DS-RM24C32DS–117B–11/2016
2
1.
Block Diagram
Figure 1-1. Block Diagram
VCC
I/O Buffers and Data
Latches
SCL
SDA
I/O
Control
Logic
Page Buffer
E0
E1
E2
WP
Memory
Control
Logic
Y-Decoder
GND
Address
Latch
&
Counter
X-Decoder
256 Kb
Resistive Memory
RM24C32DS
DS-RM24C32DS–117B–11/2016
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2.
Pin/Signal Descriptions
Table 2-1.
Symbol
Pin/Signal Descriptions
Pin #
Name/Function
Description
LSB of the three external enable bits (E0, E1 and E2). The levels of
the external enable bits are compared with three enable bits in the
received control byte to provide device selection. The device is
selected if the comparison is true. Up to eight devices may be
connected to the same bus by using different E0, E1, E2
combinations.
The middle of the three external enable bits (E0, E1 and E2). The
levels of the enable bits are compared with three enable bits in the
received control byte to provide device selection. Also see the E0,
E2 pin.
MSB of the three external enable bits (E0, E1 and E2). The levels
of the enable bits are compared with three enable bits in the
received control byte to provide device selection. Also see the E0,
E1 pin.
E0
1
LSB - Least Significant Bit,
External Enable
E1
2
External Enable
E2
3
MSB - Most Significant Bit,
External Enable
Ground
GND
4
SDA
5
Serial Data
Bidirectional pin used to transfer addresses and data into and data
out of the device. It is an open-drain terminal, and therefore
requires a pull-up resistor to VCC. Typical pull-up resistors are:
10KΩ for 100KHz, and 2KΩ for 400KHz and 1MHz.
For normal data transfer, SDA is allowed to change only during SCL
low. Changes during SCL high are reserved for indicating the
START and STOP conditions.
SCL
6
Serial Clock
This input is used to synchronize the data transfer from and to the
device. SCL is an input only, since it is a slave-only device.
Connect to either VCC or GND. If pulled low, write operations are
enabled. If pulled high, write operations are inhibited, but read
operations are not affected.
Power supply pin
WP
Vcc
7
8
Write Protect
Power
2.1
2.1.1
Pin Out Diagram
Pinouts
8-Lead SOIC, TSSOP and 8-pad UDFN (Top View)
WLCSP (Contact Adesto)
RM24C32DS
DS-RM24C32DS–117B–11/2016
4
3.
I
2
C Bus Protocol
I
2
C is a 2-wire serial bus architecture with a clock pin (SCL) for synchronization, and a data pin (SDA) for data transfer.
On the device the SDA pin is bi-directional. The SCL pin is an input only, because the device is slave-only. The SCL and
SDA pins are both externally connected to a positive supply voltage via a current source or pull-up resistor. When the bus
is free, both lines are high. The output stages of devices connected to the bus must have an open drain or open collector
to perform a wired-AND function. Data on the I
2
C bus can be transferred at rates of up to 1 Mbit/s. The number of
interfaces that may be connected to the bus is solely dependent on the bus capacitance limit of 400pF.
The data on the SDA line must be stable during the high period of the clock. The high or low state of the data line can
only change when the clock signal on the SCL line is low (see Figure 1-1).
Figure 3-1. Bit Transfer on the I
2
C bus
A high-to-low transition on the SDA line while SCL is high indicates a START condition. A low-to-high transition on the
SDA line while SCL is high defines a STOP condition.
START and STOP conditions are always generated by the master. The bus is considered to be busy after the START
condition. The bus is considered to be free again a certain time after the STOP condition (see Figure 3-2).
Figure 3-2. START and STOP conditions
Every byte put on the SDA line must be 8 bits long. The number of bytes that can be transmitted per transfer is
unrestricted. Each byte must be followed by an acknowledge bit; therefore, the number of clock cycles to transfer one
byte is nine. Data is transferred with the most significant bit (MSB) first.
RM24C32DS
DS-RM24C32DS–117B–11/2016
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