Si4702/03-D30
B
R O A D C A S T
F M R
A D I O
T
U N E R FOR
P
O R TA B L E
A
P P L I C A T I O N S
Features
This data sheet applies to
Si4702/03-D Firmware 30 and
greater
Worldwide FM band support
(64–108 MHz)
Digital low-IF receiver
Frequency synthesizer with
integrated VCO
Seek tuning
Automatic frequency control (AFC)
Automatic gain control (AGC)
Excellent overload immunity
Signal strength measurement
Programmable de-emphasis
(50/75 µs)
Adaptive noise suppression
Volume control
Line-level analog output
32.768 kHz reference clock
2-wire and 3-wire control
interface
2.7 to 5.5 V supply voltage
Integrated LDO regulator
allows direct connection to
battery
3 x 3 mm 20-pin QFN package
Ordering Information:
See page 38.
Pb-free/RoHS compliant
RDS/RBDS Processor (Si4703)
Integrated crystal oscillator
Pin Assignments
(Top View)
Si4702/03-GM
GPIO1
GPIO2
GPIO3
17
10
V
IO
NC
Applications
Cellular handsets
MP3 players
Portable radios
USB FM radio
PDAs
Notebook PCs
Portable navigation
Consumer electronics
NC
FMIP
RFGND
GND
RST
1
2
3
4
5
6
SEN
20
19
18
Description
The Si4702/03 integrates the complete tuner function from antenna input
to stereo audio output for FM broadcast radio reception.
GND
PAD
7
SCLK
8
SDIO
9
RCLK
Functional Block Diagram
Headphone
Cable
FMIP
RFGND
LNA
PGA
Q
ADC
I
ADC
Si4702/03
DAC
FILTER
DEMOD
MPX
AUDIO
AMPLIFIER
DSP
LOUT
U.S. and International
Patents Pending
Abbreviated U.S. patent list:
7272375, 7127217, 7272373,
7272374, 7321324, 7339503,
7339504, 7355476, 7426376,
7436252, 7471940
DAC
ROUT
AGC
32.768 kHz
0 / 90
LOW-IF
GPIO
GPIO
VIO
CONTROL
INTERFACE
RCLK
2.7–5.5 V
VA
VD
TUNE
AFC
RDS
(Si4703)
RST
SDIO
SCLK
SEN
REG
XTAL
OSC
RSSI
Rev. 0.6 7/09
Copyright © 2009 by Silicon Laboratories
CONTROLLER
Si4702/03-D30
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Silicon Laboratories Confidential. Information contained herein is covered under non-disclosure agreement (NDA).
V
A
16
15 GND
14 LOUT
13 ROUT
12 GND
11 V
D
Si4702/03-D30
T
ABLE
Section
OF
C
ONTENTS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2. FM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4.3. General Purpose I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.4. RDS/RBDS Processor and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.5. Stereo Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.6. Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.7. Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.8. Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.9. Reset, Powerup, and Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.10. Audio Output Summation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.11. Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.12. Programming Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5. Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6. Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
7. Pin Descriptions: Si4702/03-D30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9. Package Markings (Top Marks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9.1. Si4702 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9.2. Si4703 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9.3. Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
10. Package Outline: Si4702/03-D30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
11. PCB Land Pattern: Si4702/03-D30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Additional Reference Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Rev. 0.6
3
Si4702/03-D30
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Digital Supply Voltage
Analog Supply Voltage
Interface Supply Voltage
Digital Power Supply Power-Up
Rise Time
Analog Power Supply Power-Up
Rise Time
Interface Power Supply Power-Up
Rise Time
Ambient Temperature
Symbol
V
D
V
A
V
IO
V
DRISE
V
ARISE
V
IORISE
T
A
Test Condition
Min
2.7
2.7
1.62
10
10
10
–20
Typ
—
—
—
—
—
—
25
Max
5.5
5.5
3.6
—
—
—
85
Unit
V
V
V
µs
µs
µs
°C
Note:
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at V
D
= V
A
= 3.3 V and 25 °C unless otherwise stated. Parameters are tested in production unless
otherwise stated.
Table 2. Absolute Maximum Ratings
1,2
Parameter
Digital Supply Voltage
Analog Supply Voltage
Interface Supply Voltage
Input Current
3
Input Voltage
3
Operating Temperature
Storage Temperature
RF Input Level
4
Symbol
V
D
V
A
V
IO
I
IN
V
IN
T
OP
T
STG
Value
–0.5 to 5.8
–0.5 to 5.8
–0.5 to 3.9
±10
–0.3 to (V
IO
+ 0.3)
–40 to 95
–55 to 150
0.4
Unit
V
V
V
mA
V
°C
°C
V
pK
Notes:
1.
Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure beyond
recommended operating conditions for extended periods may affect device reliability.
2.
The Si4702/03-D30 device is a high-performance RF integrated circuit with an ESD rating of < 2 kV HBM. Handling
and assembly of this device should only be done at ESD-protected workstations.
3.
For input pins SCLK, SEN, SDIO, RST, RCLK, GPIO1, GPIO2, and GPIO3.
4.
At RF input pins.
4
Rev. 0.6
Si4702/03-D30
Table 3. DC Characteristics
(V
D
= V
A
= 2.7 to 3.6 V, V
IO
= 1.62 to 3.6 V, T
A
= –20 to 85 °C)
Parameter
FM Receiver to Line Output
V
DD
Supply Current
V
DD
Supply Current
1
V
DD
RDS Supply Current
2
Supplies and Interface
Interface Supply Current
Digital Powerdown Current
Analog Powerdown Current
V
IO
Powerdown Current
High Level Input Voltage
3
Low Level Input Voltage
3
High Level Input Current
3
Low Level Input Current
3
High Level Output Voltage
4
Low Level Output Voltage
4
Symbol
Test Condition
Min
Typ
Max
Unit
I
FM
I
FM
I
FM
Low SNR level
—
—
—
15
17.7
16.7
—
—
—
mA
mA
mA
I
IO
I
DDPD
I
APD
I
IOPD
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
V
IN
= V
IO
= 3.6 V
V
IN
= 0 V,
V
IO
= 3.6 V
I
OUT
= 500 µA
I
OUT
= –500 µA
Enable = 0
SCLK, RCLK inactive
—
—
—
—
0.7 x V
IO
–0.3
–10
–10
0.8 x V
IO
—
300
2.5
3.5
2.5
—
—
—
—
—
—
—
—
—
—
V
IO
+ 0.3
0.3 x V
IO
10
10
—
0.2 x V
IO
µA
µA
µA
µA
V
V
µA
µA
V
V
Notes:
1.
LNA is automatically switched to higher current mode for optimum sensitivity in weak signal conditions.
2.
Guaranteed by characterization.
3.
For input pins SCLK, SEN, SDIO, RST, RCLK, DCLK, DFS, GPO1, GPO2, and GPO3.
4.
For output pins SDIO, DOUT, GPO1, GPO2, and GPO3.
Rev. 0.6
5
stm32/stm8
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