Device
Engineering
Incorporated
385 East Alamo Drive
Chandler, AZ 85225
Phone: (480) 303-0822
Fax: (480) 303-0824
E-mail: admin@deiaz.com
DEI1066
OCTAL GND/OPEN INPUT, SERIAL
OUTPUT INTERFACE IC
FEATURES
•
Eight GND/OPEN discrete inputs
o
Meet electrical requirements for ABD0100 GND/OPEN discrete input.
o
Hysteresis provides noise immunity
o
Internal pull up resistor with 1mA source current to prevent dry relay contacts.
o
Internal isolation diode
o
Inputs protected from Lightning Induced Transients per DO160D, Section 22, Cat A3 and B3.
3-wire serial interface (/CS, CLK, DO)
o
Direct interface to Serial Peripheral Interface (SPI) port.
o
TTL/CMOS compatible inputs and Tristate output
o
10MHz Data Rate
o
Serial input to expand Shift Register
Logic Supply Voltage (VCC):
3.3V or 5V
Analog Supply Voltage (VDD):
5V to 18V
16L NB SOIC package
16L Ceramic SO Package
•
•
•
•
•
PIN ASSIGNMENTS
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
DIN7
DIN8
1
16
VDD
GND
VCC
GND
SDIN
/CS
SCLK
DOUT
DEI1066
Figure 1 DEI1066 Pin Assignment (16 Lead NB SOIC)
©2008 Device Engineering Inc
Page 1 of 12
DS-MW-01066-01 Rev G
03/20/09
FUNCTIONAL DESCRIPTION
The DEI1066 is an eight-channel discrete-to digital interface BICMOS device. It senses eight Ground/Open discrete signals of
the type commonly found in avionic systems. The data is read from the device via an eight-bit serial shift register with 3-state
output. This serial interface is compatible with the industry standard Serial Peripheral Interface (SPI) bus.
Table 1 Pin Descriptions
Pins
8-1
9
10
11
Name
DIN[8:1]
DOUT
SCLK
/CS
Description
Parallel data inputs. Eight Ground/Open format discrete signals. These
have an internal pull-up to VDD. The logic threshold and hysteresis
characteristics are determined by the applied VDD voltage.
Serial data output. This pin is the output from the last stage of the shift
register. This is a 3-state output.
Serial Shift Clock. A low-to-high transition on this input shifts data on
the serial data input into the shift register and data in stage 8 is shifted out
DOUT, being replaced by the data previously stored in stage 7.
Chip Select. A high-to-low transition on this input loads data from the
parallel DIN[8:1] inputs into the shift register. A low level on this input
enables the DOUT 3-state output and the shift register. A high level on
this input forces DOUT to the high impedance state and disables the shift
register so SCLK transitions have no effect.
Serial Data Input. Data on this input is shifted into the shift register on
the rising edge of the SCLK input if the /CS input is low. This input has
an internal pull-down resistor to GND.
Logic Ground.
Logic Supply Voltage.
Analog Ground.
Analog Supply Voltage.
12
13
14
15
16
SDIN
GND
VCC
GND
VDD
SDIN
SDIN
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
DIN7
DIN8
INPUT RESISTORS,
COMPARATORS,
FILTERING, AND
LIGHTNING
PROTECTION
(8 CHANNELS)
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
Q8
DOUT
SHIFT REG
SCLK
/CS
SCK
SH/LD
Figure 2 DEI1066 LOGIC DIAGRAM
©2008 Device Engineering Inc
Page 2 of 12
DS-MW-01066-01 Rev G
03/20/09
Vdd
Typical DINn Threshold Voltage & Hystersis
DIN Threshold Voltage (V)
R1
2K
Vdd
DINn
R2
12K
Comparator
with RC
filter
D1
Vout
(to Shift Reg)
Vdd
Reference
and
Hysteresis
18
16
14
12
10
8
6
4
2
0
0
5
10
15
20
Vdd Supply Voltage (V)
Vth+
Vth-
Figure 3 DINn Input Circuit
Figure 4 DIN Threshold vs Vdd
Table 2 Truth Table
/CS
1
↓
0
0
0
↑
SCLK
X
X
↑
↑
↓
X
SDIN
X
X
0
1
X
X
DIN[8:1]
X
Sampled into Shift
Register
X
X
X
X
SREG Q1
X
DIN1
0
1
No Change
No Change
DOUT
HI-Z
Enabled
DIN8
SREG Q8
SREG Q8
No Change
Disabled to HI-Z
DIN[8:1] Input Structure
Each of the eight discrete inputs consist of the circuit shown in Figure 3. Each DINn signal is conditioned by the resistor /
diode network and presented to the comparator IN+. The reference and hysteresis voltage is developed at the comparator IN-.
Some notable features are:
•
•
When Vdd is +15V, the circuit shall source >1mA to a grounded input. This current will prevent a “dry” relay
contact.
The input threshold voltage and hysteresis varies with the Vdd supply.
o
For Vdd of +5V, the falling Vth > 3.5V.
o
For Vdd of +15V, the rising Vth < 14V.
o
For Vdd of +18V, the rising Vth < 15.4V.
o
Hysteresis is approximately as shown in Figure 4.
o
The input thresholds vary with Vdd supply voltages and can be approximated as follows:
For Vdd = 5V to 18V
•
Vlh_max = 0.98*Vdd – 0.65V
•
Vhl_min = 0.95*Vdd – 0.8V
The comparator includes an RC filter to provide noise rejection of transient pulses of up to several uS. Thus there is a
relatively large DINx setup time of several uS (Refer to timing parameter tsu2).
The inputs can withstand continuous input voltages of 40V minimum. The isolation diode breakdown voltage is
greater than 50V. The 12K Ohm input resistor is designed to limit diode breakdown current to safe levels during
transient events.
•
•
©2008 Device Engineering Inc
Page 3 of 12
DS-MW-01066-01 Rev G
03/20/09
Serial Interface and Shift Register
The DEI1066 digital interface is an 8-Bit Serial or Parallel-Input / Serial-Output Shift Register with 3-State Output. The
control inputs to the shift register are connected as shown in Figure 2 DEI1066 LOGIC DIAGRAM to implement an SPI
compatible bus consisting of /CS, SCLK, DOUT, and SDIN. The Figure 5 waveform depicts a typical 8-Bit read cycle where
the 8 DIN signals are read on to the serial bus. The Figure 6 waveform demonstrates a daisy-chain application where a 16-Bit
read cycle includes the serial data passed through from the SDIN input.
/CS
SCLK
DIN[8:1]
SDIN
DOUT
X
X
X
VALID
X
X
X
DIN8
DIN7
DIN6
DIN5
DIN4
DIN3
DIN2
DIN1
DIN inputs latched in S-Reg
Figure 5 Serial Bus Read Cycle, 8 Bit
/CS
SCLK
DIN[8:1]
SDIN
DOUT
X
X
X
VALID
X
X
SI8
SI7
SI6
SI5
SI4
SI3
SI2
SI1
X
DIN8
DIN7
DIN6
DIN5
DIN4
DIN3
DIN2
DIN1
SI8
SI7
SI6
SI5
SI4
SI3
SI2
SI1
Figure 6 Serial Bus Read Cycle, 16 Bit Daisy Chain
©2008 Device Engineering Inc
Page 4 of 12
DS-MW-01066-01 Rev G
03/20/09
Lightning Protection
DINn inputs are designed to survive lightning induced transients as defined by RTCA DO160D, Section 22, Cat A3 and B3,
Waveforms 3, 4, and 5A, Level 3. See waveforms below.
V/I
25% to 75%
of Largest Peak
50%
V
Peak
T1 = 6.4uS
T2 = 70uS
0
t
50%
F = 1MHZ and 10MHZ
Figure 7 Voltage / Current Waveform 3
0
T1
T2
t
Figure 8 Voltage Waveform 4
V/I
Peak
Waveform Source Impedance characteristics:
•
Waveform 3 Voc/Isc = 600V / 24A => 25 Ohms
•
Waveform 4 Voc/Isc = 300 V / 60 A => 5 Ohms
•
Waveform 5A Voc / Isc = 300V / 300A => 1 Ohm
50%
T1=40uS
T2=120uS
0
T1
T2
t
Figure 9 Current/Voltage Waveform 5A
©2008 Device Engineering Inc
Page 5 of 12
DS-MW-01066-01 Rev G
03/20/09
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
