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INTEGRATED CIRCUITS
74AVC16334A
16-bit registered driver with
inverted register enable and
Dynamic Controlled Outputs™ (3-State)
Product specification
Supersedes data of 2000 May 02
2000 Aug 03
Philips
Semiconductors
Philips Semiconductors
Product specification
16-bit registered driver with inverted register enable and
Dynamic Controlled Outputs™ (3-State)
74AVC16334A
FEATURES
•
Wide supply voltage range of 1.2 V to 3.6 V
•
Complies with JEDEC standard no. 8-1A/5/7.
•
CMOS low power consumption
•
Input/output tolerant up to 3.6 V
•
DCO (Dynamic Controlled Output) circuit dynamically changes
output impedance, resulting in noise reduction without speed
degradation
PIN CONFIGURATION
OE
Y
0
Y
1
GND
Y
2
Y
3
V
CC
Y
4
Y
5
GND
Y
6
Y
7
Y
8
Y
9
GND
Y
10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
CP
A
0
A
1
GND
A
2
A
3
V
CC
A
4
A
5
GND
A
6
A
7
A
8
A
9
GND
A
10
A
11
V
CC
A
12
A
13
GND
A
14
A
15
LE
•
Low inductance multiple V
CC
and GND pins for minimum noise
and ground bounce
•
Power off disables 74AVC16334A outputs, permitting Live
•
Integrated input diodes to minimize input overshoot and
•
Full PC133 solution provided when used with PCK2509S or
PCK2510S and CBT16292
undershoot
Insertion
DESCRIPTION
The 74AVC16334A is a 16-bit universal bus driver. Data flow is
controlled by output enable (OE), latch enable (LE) and clock inputs
(CP).
This product is designed to have an extremely fast propagation
delay and a minimum amount of power consumption.
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pullup resistor (Live
Insertion).
A Dynamic Controlled Output (DCO) circuitry is implemented to
support termination line drive during transient. See the graphs on
page 8 for typical curves.
Y
11
V
CC
Y
12
Y
13
GND
Y
14
Y
15
NC
SH00167
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25°C; t
r
= t
f
≤
2.0 ns; C
L
= 30 pF.
SYMBOL
t
PHL
/t
PLH
PARAMETER
Propagation delay
An to Yn
Propagation delay
LE to Yn;
CP to Yn
Input capacitance
Power dissipation capacitance per buffer
V
I
= GND to V
CC1
Outputs enabled
Output disabled
V
CC
= 1.8 V
V
CC
= 2.5 V
V
CC
= 3.3 V
V
CC
= 1.8 V
V
CC
= 2.5 V
V
CC
= 3.3 V
CONDITIONS
TYPICAL
2.5
1.7
1.5
2.7
2.0
1.6
3.8
25
6
UNIT
ns
t
PHL
/t
PLH
C
I
C
PD
ns
pF
pF
NOTE:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+
S
(C
L
×
V
CC2
×
f
o
) where: f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
S
(C
L
×
V
CC2
×
f
o
) = sum of outputs.
ORDERING INFORMATION
PACKAGES
48-Pin Plastic Thin Shrink Small Outline (TSSOP) Type II
TEMPERATURE
RANGE
–40°C to +85°C
OUTSIDE NORTH
AMERICA
AVC16334A DGG
NORTH AMERICA
DRAWING
NUMBER
SOT362-1
2000 Aug 03
2
853-2212 24282
Philips Semiconductors
Product specification
16-bit registered driver with inverted register enable and
Dynamic Controlled Outputs™ (3-State)
74AVC16334A
PIN DESCRIPTION
PIN NUMBER
24
2, 3, 5, 6, 8, 9, 11, 12, 13,
14, 16, 17, 19, 20, 22, 23
4, 10, 15, 21, 28, 34, 39,
45
7, 18, 31, 42
1
25
48
47, 46, 44, 43, 41, 40,
38, 37, 36, 35, 33, 32,
30, 29, 27, 26
SYMBOL
NC
Y
0
to Y
15
GND
V
CC
OE
LE
CLK
A
0
to A
15
NAME AND FUNCTION
No connection
Data outputs
Ground (0 V)
LOGIC SYMBOL (IEEE/IEC)
OE
CP
LE
1
48
25
C3
G2
Y
0
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
11
∇
1
3D
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
EN1
2C3
Positive supply voltage
Output enable input
(active LOW)
Latch enable input
(active LOW)
Clock input
Data inputs
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
Y
8
Y
9
Y
10
LOGIC SYMBOL
Y
11
Y
12
Y
13
OE
Y
14
Y
15
CP
SH00168
FUNCTION TABLE
INPUTS
OE
LE
LE
X
L
L
H
H
H
CLK
X
X
X
↑
↑
L or H
A
X
L
H
L
H
X
OUTPUTS
Z
L
H
L
H
Y
01
H
L
L
A
1
D
LE
CP
Y
1
L
L
L
H
L
X
Z
↑
SH00202
TO THE 17 OTHER CHANNELS
=
=
=
=
=
HIGH voltage level
LOW voltage level
Don’t care
High impedance “off” state
LOW-to-HIGH level transition
NOTE:
1. Output level before the indicated steady-state input conditions
were established.
2000 Aug 03
3
Philips Semiconductors
Product specification
16-bit registered driver with inverted register enable and
Dynamic Controlled Outputs™ (3-State)
74AVC16334A
168-pin SDR SDRAM DIMM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
BACK SIDE
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
FRONT SIDE
74AVC16334A 74AVC16334A 74AVC16334A
PCK2509S or PCK2510S
The PLL clock distribution device and AVC registered drivers reduce
signal loads on the memory controller and prevent timing delays and
waveform distortions that would cause unreliable operation
SDRAM
SW00525
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
CC
V
CC
V
I
V
O
T
amb
t
r
, t
f
PARAMETER
DC supply voltage
(according to JEDEC Low Voltage Standards)
DC supply voltage (for low voltage applications)
DC Input voltage range
DC output voltage range; output 3-State
DC output voltage range; output HIGH or LOW state
Operating free-air temperature range
Input rise and fall times
V
CC
= 1.65 to 2.3 V
V
CC
= 2.3 to 3.0 V
V
CC
= 3.0 to 3.6 V
CONDITIONS
MIN
1.65
2.3
3.0
1.2
0
0
0
–40
0
0
0
MAX
1.95
2.7
3.6
3.6
3.6
3.6
V
CC
+85
30
20
10
UNIT
V
V
V
V
°C
ns/V
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0 V).
SYMBOL
V
CC
I
IK
V
I
I
OK
V
O
V
O
I
O
I
GND
, I
CC
T
stg
P
TOT
PARAMETER
DC supply voltage
DC input diode current
DC input voltage
DC output diode current
DC output voltage; output 3-State
DC output voltage; output HIGH or LOW state
DC output source or sink current
DC V
CC
or GND current
Storage temperature range
Power dissipation per package
–plastic thin-medium-shrink (TSSOP)
For temperature range: –40 to +125
°C
above +55°C derate linearly with 8 mW/K
V
I
t0
For data inputs
1
V
O
uV
CC
or V
O
t
0
Note 1
Note 1
V
O
= 0 to V
CC
CONDITIONS
RATING
–0.5 to +4.6
–50
–0.5 to 4.6
"50
–0.5 to 4.6
–0.5 to V
CC
+0.5
"50
"100
–65 to +150
600
UNIT
V
mA
V
mA
V
V
mA
mA
°C
mW
NOTE:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2000 Aug 03
4
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