Device
Engineering
Incorporated
385 E. Alamo Dr.
Chandler, AZ 85225
Phone: (480) 303-0822
Fax: (480) 303-0824
E-mail: admin@deiaz.com
DEI1166
OCTAL GND/OPEN INPUT,
PARALLEL OUTPUT INTERFACE IC
FEATURES
Eight GND/OPEN discrete inputs
o
Meet electrical requirements for ABD0100 GND/OPEN discrete input.
o
Hysteresis provides noise immunity.
o
Internal pull up resistor with 1mA source current to prevent dry relay contacts.
o
Internal isolation diode
o
Inputs protected from Lightning Induced Transients per DO160D, Section 22, Cat A3 and B3.
3.3V or 5V TTL/CMOS compatible digital IO
o
8 tri-state outputs
o
/CS & /OE control inputs
Logic Supply:
3.3V or 5V
Analog Supply:
5V to 18V
24L TSSOP package
PIN ASSIGNMENTS
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
DIN7
DIN8
NC
NC
/CS
/OE
1
2
3
4
5
6
7
8
9
10
11
12
24
DO1
DO2
GND
DO3
DO4
VCC
DO5
DO6
DO7
DO8
GND
VDD
DEI1166
23
22
21
20
19
18
17
16
15
14
13
Figure 1 DEI1166 Pin Assignment (24 Lead TSSOP)
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Table 1 Pin Descriptions
Pins
8-1
Name
DIN[8:1]
Description
Discrete Inputs. Eight Ground/Open format discrete signals. These have an
internal pull-up to VDD. The threshold and hysteresis characteristics are
determined by the applied VDD voltage.
Not Connected.
Chip Select Logic Input. Low input selects the device.
Output Enable Logic Input. Low input when /CS is low will enable the tri-
state outputs.
Analog Supply. +5 to +18V
Analog Ground.
Logic Supply. +3.3V or +5V
Logic Ground.
Logic Outputs. Eight tri-state data outputs.
9-10
11
12
13
14
19
22
15,16,17,18,20,21,23,24
NC
/CS
/OE
VDD
GND
VCC
GND
DO[8:1]
FUNCTIONAL DESCRIPTION
The DEI1166 is an eight-channel parallel-output discrete-to-digital interface BICMOS device. It senses eight Ground/Open
discrete signals of the type commonly found in avionic systems. The data is read from the device via a parallel 3-state output.
O E
CE
V
DD
D IN 1
12K
VCC
2K
+
2K
12K
T HR E SH O LD
AND
H Y S T E R S IS
-
DO1
D IN 2
2K
12K
TH R E S H O L D
AND
H Y S T E R S IS
+
-
+
DO2
D IN 3
2K
12 K
TH R ES HO LD
AN D
H Y S TE R S I S
-
+
DO 3
D IN 4
2K
TH R ES HO LD
AN D
H Y S TE R S I S
-
+
DO4
D IN 5
12K
TH R ES HO LD
AN D
H Y S TE R S I S
2K
-
DO5
D IN 6
12 K
+
2K
TH R E S H O L D
AND
H Y S T E R S IS
-
DO 6
D IN 7
12 K
+
2K
TH R ES HO LD
AN D
H Y S TE R S I S
-
DO 7
D IN 8
12K
TH R ES H OL D
AN D
H Y S T E R S IS
+
-
DO 8
G ND
Figure 2 DEI1166 Function Diagram
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Table 2 Truth Table
/CE
L
L
H
X
/OE
L
L
X
H
DIN[8:1]
Open
Ground
X
X
DO[8:1]
L
H
High Z
High Z
Figure 3 Discrete Input Circuit
DIN[8:1] INPUT STRUCTURE
Each of the eight discrete inputs consists of the circuit in Figure 3. This circuit compares two voltages, one generated
internally, and one a function of an external pin, DIN. The voltage applied to DIN divided by 7, and offset by +13V, so the
input at DIN must be approximately 7V, so that the internal voltage to the comparator, Comp-IN, is 14V, 7 / 7 +13. The
comparator will change states, and also change the internal reference from 14V to 13.6V. This reinforces the switching
(hysteresis), such that the DIN input must be lowered from 7V to 4.2V to again switch the comparator.
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The actual switch limits are dependent on VDD, as shown below, but are independent of VCC. The divider ratio remains fixed,
however, the offset changes proportional to VDD.
Figure 4 DIN Threshold vs. Vdd
Figure 5 depicts the resistance value that when applied between the input and ground, causes the comparator to switch. Lower
effective R_Din values can be achieved by adding an external diode isolated pull-up resistor to Vdd (or higher) supply.
Figure 5 Input switching resistance
DEI reserves the right to make changes to any products or specifications herein. DEI makes no warranty, representation, or
guarantee regarding suitability of its products for any particular purpose.
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LIGHTNING PROTECTION
DINn inputs are designed to survive lightning induced transients as defined by RTCA DO160D, Section 22, Cat A3 and B3,
Waveforms 3, 4, and 5A, Level 3. See waveforms below.
V/I
25% to 75%
of Largest Peak
50%
V
Peak
T1 = 6.4us
T2 = 70us
t
0
50%
F = 1MHZ and 10MHZ
0
T1
t
T2
Figure 6 Voltage / Current Waveform 3
Figure 7 Voltage / Current Waveform 4
V/I
Peak
Waveform Source Impedance characteristics:
Waveform 3 Voc/Isc = 600V / 24A => 25 Ohms
Waveform 4 Voc/Isc = 300 V / 60 A => 5 Ohms
Waveform 5A Voc / Isc = 300V / 300A => 1 Ohm
50%
T1=40us
T2=120us
0
T1
T2
t
Figure 8
Voltage / Current
Waveform 5A
NOTE
It is possible to achieve higher level lightning immunity by adding a 1K Ohm series resistor and a Transient Voltage
Suppressor (TVS) to clamp the inputs below 600V. The 1K Ohm resistance reduces the input threshold. For
example, with Vdd = 15V, the thresholds become:
Max LH threshold = 15.3V
Min HL threshold = 11.3V
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