Si5020
SiPHY™ M
ULTI
-R
ATE
SONET/SDH C
LOCK AND
D
ATA
R
ECOVERY
IC
Features
Complete high-speed, low-power, CDR solution includes the following:
!
!
!
!
!
Supports OC-48/12/3, STM-16/4/1,
!
Gigabit Ethernet, and 2.7 Gbps FEC
Low Power—270 mW (TYP OC-48)
!
Small footprint: 4 mm x 4 mm
DSPLL™ eliminates external loop
!
filter components
!
3.3 V tolerant control inputs
!
Exceeds all SONET/SDH jitter
specifications
Jitter generation
2.9 mUI
rms
(Typ)
Device powerdown
Loss-of-lock indicator
Single 2.5 V Supply
Ordering Information:
See page 18.
Applications
Pin Assignments
!
RATESEL1
RATESEL0
CLKOUT+
Description
REXT
1
2
3
4
5
20 19 18 17 16
15
PWRDN
VDD
DOUT+
DOUT–
VDD
The Si5020 is a fully-integrated low-power clock and data recovery (CDR)
IC designed for high-speed serial communication systems. It extracts
timing information and data from a serial input at OC-48/12/3, STM-16/4/1,
or Gigabit Ethernet (GbE) rates. Support for 2.7 Gbps data streams is also
provided for OC-48/STM-16 applications that employ forward error
correction (FEC). DSPLL technology eliminates sensitive noise entry
points, making the PLL less susceptible to board-level interaction and
helping to ensure optimal jitter performance.
The Si5020 represents a new standard in low jitter, low power, and small
size for high-speed CDRs. It operates from a single 2.5 V supply over the
industrial temperature range (–40 to 85 °C).
VDD
GND
REFCLK+
REFCLK–
CLKOUT–
14
13
12
11
10
DIN–
GND
Pad
Connection
6
LOL
7
VDD
GND
8
GND
SONET/SDH/ATM routers
!
Add/drop multiplexers
!
Digital cross connects
!
Gigabit Ethernet interfaces
!
SONET/SDH test equipment
!
Optical transceiver modules
!
SONET/SDH regenerators
!
Board level serial links
Si5020
9
DIN+
Top View
Functional Block Diagram
LOL
D IN +
D IN –
2
BU F
D SPLL
TM
Phas e-Locked
Loop
R etim er
BU F
2
D OU T +
D OU T –
PW R D N /C AL
Bias
2
2
BU F
2
C LKOU T +
C LKOU T –
R EXT
R ATESEL1-0
R EF C LKIN +
R EF C LKIN –
Rev. 1.4 1/04
Copyright © 2004 by Silicon Laboratories
Si5020-DS14
Si5020
T
A B L E
Section
OF
C
O N T E N TS
Page
Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
DSPLL™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
PLL Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Multi-Rate Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Reference Clock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Forward Error Correction (FEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Lock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Device Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Pin Descriptions: Si5020 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Package Outline: Si5020-BM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4x4 mm 20L MLP Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Rev. 1.4
3
Si5020
Detailed Block Diagram
Retim e
DOUT+
DOUT–
c
DIN+
DIN–
Phase
Detector
A/D
DSP
n
VCO
CLK
Divider
CLKOUT+
c
CLKOUT–
REFCLK+
REFCLK–
2
RATESEL1-0
REXT
Bias
G eneration
Calibration
Lock
Detector
LOL
PWRDN/CAL
4
Rev. 1.4
Si5020
Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Temperature
Si5020 Supply Voltage
2
Symbol
T
A
V
DD
Test Condition
Min
1
–40
2.375
Typ
25
2.5
Max
1
85
2.625
Unit
°C
V
Notes:
1.
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated.
2.
The Si5020 specifications are guaranteed when using the recommended application circuit (including component
tolerance) shown in "Typical Application Schematic" on page 10.
V
SIGNAL+
Differential
V
ICM
, V
OCM
SIGNAL–
I/Os
V
IS
Single-Ended Voltage
(SIGNAL+) – (SIGNAL–)
Differential
Voltage Swing
V
ID
,V
OD
(V
ID
= 2 V
IS
)
Differential Peak-to-Peak Voltage
t
Figure 1. Differential Voltage Measurement (DIN, REFCLK, DOUT, CLKOUT)
t
C-D
DOUT
CLKOUT
Figure 2. Differential Clock to Data Timing
DOUT,
CLK OUT
t
F
t
R
80%
20%
Figure 3. Differential DOUT and CLKOUT Rise/Fall Times
Rev. 1.4
5
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