Features
•
•
•
•
•
•
•
•
80C52 Compatible
8051 pin and instruction compatible
Four 8-bit I/O ports
Three 16-bit timer/counters
256 bytes scratchpad RAM
High-Speed Architecture
40 MHz @ 5V, 30MHz @ 3V
X2 Speed Improvement capability (6 clocks/machine cycle)
– 30 MHz @ 5V, 20 MHz @ 3V (Equivalent to
– 60 MHz @ 5V, 40 MHz @ 3V)
Dual Data Pointer
On-chip ROM/EPROM (16K-bytes, 32K-bytes)
Programmable Clock Out and Up/Down Timer/Counter 2
Hardware Watchdog Timer (One-time enabled with Reset-Out)
Asynchronous port reset
Interrupt Structure with
6 Interrupt sources
4 level priority interrupt system
Full duplex Enhanced UART
Framing error detection
Automatic address recognition
Low EMI (inhibit ALE)
Power Control modes
Idle mode
Power-down mode
Power-off Flag
Once mode (On-chip Emulation)
Power supply: 4.5-5.5V, 2.7-5.5V
Temperature ranges: Commercial (0 to 70
o
C) and Industrial (-40 to 85
o
C)
Packages: PDIL40, PLCC44, VQFP44 1.4, PQFP44 F1, CQPJ44 (window), CDIL40
(window)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
8-bit CMOS
Microcontroller
16/32 Kbytes
ROM/OTP
TS80C54/58X2
TS87C54/58X2
AT80C54/58X2
AT87C54/58X2
1. Description
TS80C54/58X2 is high performance CMOS ROM, OTP and EPROM versions of the
80C51 CMOS single chip 8-bit microcontroller.
The TS8 0C54/58X2 retains a ll fe atures of the Atmel 80 C51 with e xtend ed
ROM/EPROM capacity (16/32 Kbytes), 256 bytes of internal RAM, a 6-source , 4-level
interrupt system, an on-chip oscilator and three timer/counters.
In addition, the TS80C54/58X2 a Hardware Watchdog Timer, a more versatile serial
channel that facilitates multiprocessor communication (EUART) and a X2 speed
improvement mechanism.
The fully static design of the TS80C54/58X2 allows to reduce system power consump-
tion by bringing the clock frequency down to any value, even DC, without loss of data.
Rev. 4431E–8051–04/06
The TS80C54/58X2 has 2 software-selectable modes of reduced activity for further reduction in
power consumption. In the idle mode the CPU is frozen while the timers, the serial port and the
interrupt system are still operating. In the power-down mode the RAM is saved and all other
functions are inoperative.
PDIL40
PLCC44
PQFP44 F1
VQFP44 1.4
TS80C54X2
TS80C58X2
TS87C54X2
TS87C58X2
ROM (bytes)
16k
32k
0
0
EPROM (bytes)
0
0
16k
32k
2. Block Diagram
T2EX
(1)
P3
RxD
TxD
Vcc
Vss
T2
(1)
Watch
Dog
(2) (2)
XTAL1
XTAL2
ALE/ PROG
PSEN
CPU
EA/VPP
RD
WR
(2)
(2)
Timer 0
Timer 1
INT
Ctrl
Parallel I/O Ports
Port 0 Port 1 Port 2 Port 3
EUART
RAM
256x8
ROM
/EPROM
16/32Kx8
Timer2
C51
CORE
IB-bus
(2) (2)
T0
RESET
T1
(2) (2)
P1
INT0
INT1
P0
P2
(1): Alternate function of Port 1
(2): Alternate function of Port 3
2
AT/TS8xC54/8X2
4431E–8051–04/06
AT/TS8xC54/8X2
4. SFR Mapping
The Special Function Registers (SFRs) of the TS80C54/58X2 fall into the following categories:
• C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1
• I/O port registers: P0, P1, P2, P3
• Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L,
RCAP2H
• Serial I/O port registers: SADDR, SADEN, SBUF, SCON
• Power and clock control registers: PCON
• HDW Watchdog Timer Reset: WDTRST, WDTPRG
• Interrupt system registers: IE, IP, IPH
• Others: AUXR, CKCON
3
4431E–8051–04/06
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
