512MB, 1GB (x72, ECC, SR) 184-Pin DDR SDRAM RDIMM
Features
DDR SDRAM RDIMM
MT18VDDF6472 – 512MB
1
MT18VDDF12872 – 1GB
For component data sheets, refer to Micron’s Web site:
www.micron.com
Features
• 184-pin, registered dual in-line memory module
(RDIMM)
• Fast data transfer rates: PC2100, PC2700, or PC3200
• 512MB (64 Meg x 72) and 1GB (128 Meg x 72)
• Supports ECC error detection and correction
• V
DD
= V
DD
Q = +2.5V (-40B: V
DD
= V
DD
Q = +2.6V)
• V
DDSPD
= +2.3V to +3.6V
• 2.5V I/O (SSTL_2-compatible)
• Internal, pipelined double data rate (DDR)
2n-prefetch architecture
• Bidirectional data strobe (DQS) transmitted/
received with data—that is, source-synchronous
data capture
• Differential clock inputs (CK and CK#)
• Multiple internal device banks for concurrent
operation
• Single rank
• Selectable burst lengths (BL): 2, 4, or 8
• Auto precharge option
• Auto refresh and self refresh modes: 7.8125µs
maximum average periodic refresh interval
• Serial presence-detect (SPD) with EEPROM
• Selectable CAS latency (CL) for maximum
compatibility
• Gold edge contacts
Figure 2:
R/C C (-335, -265)
PCB height: 28.58mm (1.125in)
Options
• Operating temperature
2
–
Commercial (0°C
≤
T
A
≤
+70°C)
–
Industrial (–40°C
≤
T
A
≤
+85°C)
• Package
–
184-pin DIMM (standard)
–
184-pin DIMM (Pb-free)
• Memory clock, speed, CAS latency
3
–
5.0ns (200 MHz), 400 MT/s, CL = 3
–
6.0ns (167 MHz), 333 MT/s, CL = 2.5
–
7.5ns (133 MHz), 266 MT/s, CL = 2.5
1
Marking
None
I
G
Y
-40B
-335
-265
Notes: 1. Not recommended for new designs.
2. Contact Micron for industrial temperature
module offerings.
3. CL = CAS (READ) latency; registered mode
will add one clock cycle to CL.
184-Pin RDIMM (MO-206) Figures
Figure 1:
R/C J (-40B)
PCB height: 28.58mm (1.125in)
PDF: 09005aef8074e85b/Source: 09005aef8072fe49
DDF18C64_128x72.fm - Rev. F 9/08 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
512MB, 1GB (x72, ECC, SR) 184-Pin DDR SDRAM RDIMM
Features
Table 1:
Speed
Grade
-40B
-335
-26A
-265
Key Timing Parameters
Data Rate (MT/s)
Industry
Nomenclature
PC3200
PC2700
PC2100
PC2100
Notes:
CL = 3
400
–
–
–
CL = 2.5
333
333
266
266
CL = 2
266
266
266
200
t
RCD
t
RP
t
RC
(ns)
15
18
20
20
(ns)
15
18
20
20
(ns)
55
60
65
65
Notes
1
1. The values of
t
RCD and
t
RP for -335 modules show 18ns to align with industry specifications;
actual DDR SDRAM device specifications are 15ns.
Table 2:
Parameter
Addressing
512MB
8K
8K (A0–A12)
4 (BA0, BA1)
256Mb (64 Meg x 4)
2K (A0–A9, A11)
1 (S0#)
1GB
8K
8K (A0–A12)
4 (BA0, BA1)
512Mb (128 Meg x 4)
4K (A0–A9, A11, A12)
1 (S0#)
Refresh count
Row address
Device bank address
Device configuration
Column address
Module rank address
Table 3:
Part Numbers and Timing Parameters – 512MB Modules
Base device: MT46V64M4,
1
256Mb DDR SDRAM
Part Number
2
MT18VDDF6472G-40B__
MT18VDDF6472Y-40B__
MT18VDDF6472G-335__
MT18VDDF6472Y-335__
MT18VDDF6472G-265__
Module
Density
512MB
512MB
512MB
512MB
512MB
Configuration
64 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
Module
Bandwidth
3.2 GB/s
3.2 GB/s
2.7 GB/s
2.7 GB/s
2.1 GB/s
Memory Clock/
Data Rate
5.0ns/400 MT/s
5.0ns/400 MT/s
6.0ns/333 MT/s
6.0ns/333 MT/s
7.5ns/266 MT/s
Clock Cycles
(CL-
t
RCD-
t
RP)
3-3-3
3-3-3
3-3-3
3-3-3
2.5-3-3
Table 4:
Part Numbers and Timing Parameters – 1GB Modules
Base device: MT46V128M4,
1
512Mb DDR SDRAM
Part Number
2
MT18VDDF12872G-40B__
MT18VDDF12872Y-40B__
MT18VDDF12872G-335__
MT18VDDF12872Y-335__
MT18VDDF12872G-26A__
MT18VDDF12872G-265__
MT18VDDF12872Y-265__
Notes:
Module
Density
1GB
1GB
1GB
1GB
1GB
1GB
1GB
Configuration
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
Module
Bandwidth
3.2 GB/s
3.2 GB/s
2.7 GB/s
2.7 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
Memory Clock/
Data Rate
5.0ns/400 MT/s
5.0ns/400 MT/s
6.0ns/333 MT/s
6.0ns/333 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
Clock Cycles
(CL-
t
RCD-
t
RP)
3-3-3
3-3-3
3-3-3
3-3-3
2-3-3
2.5-3-3
2.5-3-3
1. The data sheets for the base devices can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown) that designates component and
PCB revisions. Consult factory for current revision codes.
Example: MT18VDDF12872Y-335F1.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
PDF: 09005aef8074e85b/Source: 09005aef8072fe49
DDF18C64_128x72.fm - Rev. F 9/08 EN
2
512MB, 1GB (x72, ECC, SR) 184-Pin DDR SDRAM RDIMM
Pin Assignments and Descriptions
Pin Assignments and Descriptions
Table 5:
Pin Assignments
184-Pin DDR RDIMM Front
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
V
REF
DQ0
V
SS
DQ1
DQS0
DQ2
V
DD
DQ3
NC
RESET#
V
SS
DQ8
DQ9
DQS1
V
DD
Q
NC
NC
V
SS
DQ10
DQ11
CKE0
V
DD
Q
DQ16
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
DQ17
DQS2
V
SS
A9
DQ18
A7
V
DD
Q
DQ19
A5
DQ24
V
SS
DQ25
DQS3
A4
V
DD
DQ26
DQ27
A2
V
SS
A1
CB0
CB1
V
DD
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
DQS8
A0
CB2
V
SS
CB3
BA1
DQ32
V
DD
Q
DQ33
DQS4
DQ34
V
SS
BA0
DQ35
DQ40
V
DD
Q
WE#
DQ41
CAS#
V
SS
DQS5
DQ42
DQ43
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
V
DD
NC
DQ48
DQ49
V
SS
NC
NC
V
DD
Q
DQS6
DQ50
DQ51
V
SS
NC
DQ56
DQ57
V
DD
DQS7
DQ58
DQ59
V
SS
NC
SDA
SCL
184-Pin DDR RDIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
V
SS
DQ4
DQ5
V
DD
Q
DQS9
DQ6
DQ7
V
SS
NC
NC
NC
V
DD
Q
DQ12
DQ13
DQS10
V
DD
DQ14
DQ15
NC
V
DD
Q
NC
DQ20
A12
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
V
SS
DQ21
A11
DQS11
V
DD
DQ22
A8
DQ23
V
SS
A6
DQ28
DQ29
V
DD
Q
DQS12
A3
DQ30
V
SS
DQ31
CB4
CB5
V
DD
Q
CK0
CK0#
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
V
SS
DQS17
A10
CB6
V
DD
Q
CB7
V
SS
DQ36
DQ37
V
DD
DQS13
DQ38
DQ39
V
SS
DQ44
RAS#
DQ45
V
DD
Q
S0#
NC
DQS14
V
SS
DQ46
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
DQ47
NC
V
DD
Q
DQ52
DQ53
NC
V
DD
DQS15
DQ54
DQ55
V
DD
Q
NC
DQ60
DQ61
V
SS
DQS16
DQ62
DQ63
V
DD
Q
SA0
SA1
SA2
V
DDSPD
PDF: 09005aef8074e85b/Source: 09005aef8072fe49
DDF18C64_128x72.fm - Rev. F 9/08 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
512MB, 1GB (x72, ECC, SR) 184-Pin DDR SDRAM RDIMM
Pin Assignments and Descriptions
Table 6:
Symbol
A0–12
Pin Descriptions
Type
Input
Description
Address inputs:
Provide the row address for ACTIVE commands, and the column address
and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the
memory array in the respective device bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank
selected by BA0 and BA1) or all device banks (A10 HIGH). The address inputs also provide
the op-code during a MODE REGISTER SET command. BA0 and BA1 define which mode
register (mode register or extended mode register) is loaded during the LOAD MODE
REGISTER command.
Bank address:
BA0 and BA1 define the device bank to which an ACTIVE, READ, WRITE, or
PRECHARGE command is being applied.
Clock:
CK and CK# are differential clock inputs. All control, command, and address input
signals are sampled on the crossing of the positive edge of CK and the negative edge of
CK#.
Clock enable:
CKE enables (registered HIGH) and CKE disables (registered LOW) the
internal clock, input buffers, and output drivers.
Command inputs:
RAS#, CAS#, and WE# (along with S#) define the command being
entered.
Reset:
Asynchronously forces all registered outputs LOW when RESET# is LOW. This signal
can be used during power-up to ensure that CKE is LOW and DQ are High-Z.
Chip select:
S# enables (registered LOW) and disables (registered HIGH) the command
decoder.
Presence-detect address inputs:
These pins are used to configure the SPD EEPROM
address range on the I
2
C bus.
Serial clock for SPD EEPROM:
SCL is used to synchronize the presence-detect data
transfer to and from the module.
Check bits.
Data input/output:
Data bus.
Data strobe:
Output with read data. Edge-aligned with read data. Input with write data.
Center-aligned with write data. Used to capture data.
Serial data:
SDA is a bidirectional pin used to transfer addresses and data into and out of
the presence-detect portion of the module.
Power supply:
+2.5V ±0.2V.
SPD EEPROM power supply:
+2.3V to +3.6V.
SSTL_2 reference voltage (V
DD
/2).
Ground.
No connect:
These pins are not connected on the module.
BA0–BA1
CK0, CK0#
Input
Input
CKE0
RAS#, CAS#,
WE#
RESET#
S0#
SA0–SA2
SCL
CB0–CB7
DQ0–DQ63
DQS0–DQS17
SDA
V
DD
/V
DD
Q
V
DDSPD
V
REF
V
SS
NC
Input
Input
Input
Input
Input
Input
I/O
I/O
I/O
I/O
Supply
Supply
Supply
Supply
–
PDF: 09005aef8074e85b/Source: 09005aef8072fe49
DDF18C64_128x72.fm - Rev. F 9/08 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
512MB, 1GB (x72, ECC, SR) 184-Pin DDR SDRAM RDIMM
Functional Block Diagrams
Functional Block Diagrams
Figure 3:
Functional Block Diagram (R/C J, -40B)
V
SS
RS0#
DQS0
DQ0
DQ1
DQ2
DQ3
DQS1
DQ8
DQ9
DQ10
DQ11
DQS2
DQ16
DQ17
DQ18
DQ19
DQS3
DQ24
DQ25
DQ26
DQ27
DQS4
DQ32
DQ33
DQ34
DQ35
DQS5
DQ40
DQ41
DQ42
DQ43
DQS6
DQ48
DQ49
DQ50
DQ51
DQS7
DQ56
DQ57
DQ58
DQ59
DQS8
CB0
CB1
CB2
CB3
DQS CS# DM
DQ
U5
DQ
DQ
DQ
DQS CS# DM
DQ
DQ
U11
DQ
DQ
DQS17
CB4
CB5
CB6
CB7
DQS CS# DM
DQ
DQ
U20
DQ
DQ
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
Register x 2
x
x
x
x
x
x
x
x
x
2
2
2
2
2
2
2
2
2
DQS CS# DM
DQ
DQ
U10
DQ
DQ
DQS16
DQ60
DQ61
DQ62
DQ63
DQS CS# DM
DQ
DQ
U15
DQ
DQ
DQS CS# DM
DQ
U9
DQ
DQ
DQ
DQS15
DQ52
DQ53
DQ54
DQ55
DQS CS# DM
DQ
DQ
U16
DQ
DQ
DQS CS# DM
DQ
U8
DQ
DQ
DQ
DQS14
DQ44
DQ45
DQ46
DQ47
DQS CS# DM
DQ
DQ
U17
DQ
DQ
DQS CS# DM
DQ
U4
DQ
DQ
DQ
DQS13
DQ36
DQ37
DQ38
DQ39
DQS CS# DM
DQ
DQ
U18
DQ
DQ
DQS CS# DM
DQ
U3
DQ
DQ
DQ
DQS12
DQ28
DQ29
DQ30
DQ31
DQS CS# DM
DQ
DQ
U21
DQ
DQ
DQS CS# DM
DQ
U2
DQ
DQ
DQ
DQS11
DQ20
DQ21
DQ22
DQ23
DQS CS# DM
DQ
DQ
U22
DQ
DQ
DQS CS# DM
DQ
U1
DQ
DQ
DQ
DQS10
DQ12
DQ13
DQ14
DQ15
DQS CS# DM
DQ
DQ
U23
DQ
DQ
DQS9
DQ4
DQ5
DQ6
DQ7
DQS CS# DM
DQ
DQ
U24
DQ
DQ
U6, U19
RAS#
CAS#
CKE0
WE#
A0–A12
BA0, BA1
S0#
U7
RRAS#: DDR SDRAM
RCAS#: DDR SDRAM
RCKE0: DDR SDRAM
RWE#: DDR SDRAM
RA0–RA12: DDR SDRAM
RBA0, RBA1: DDR SDRAM
RS0#: DDR SDRAM
V
DDSPD
V
DD
V
REF
SDA
V
SS
CK0
CK0#
R
e
g
i
s
t
e
r
s
CK
V
DD
PLL
V
DD
SPD EEPROM
DDR SDRAM
DDR SDRAM
DDR SDRAM EEPROM
CK#
RESET#
SCL
U12
SPD EEPROM
WP A0
A1
A2
V
SS
SA0 SA1 SA2
PDF: 09005aef8074e85b/Source: 09005aef8072fe49
DDF18C64_128x72.fm - Rev. F 9/08 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
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