28(+1) Channel
High-Density T1/E1/J1
Line Interface Unit
IDT82P2828
Version 3
February 6, 2009
6024 Silver Creek Valley Road, San Jose, California 95138
Telephone: 1-800-345-7015 or 408-284-8200• TWX: 910-338-2070 • FAX: 408-284-2775
Printed in U.S.A.
© 2009 Integrated Device Technology, Inc.
DISCLAIMER
Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best pos-
sible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry
described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other
rights, of Integrated Device Technology, Inc.
LIFE SUPPORT POLICY
Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is exe-
cuted between the manufacturer and an officer of IDT.
1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform, when properly used in
accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its
safety or effectiveness.
Table of Contents
TABLE OF CONTENTS ........................................................................................................................................................... 3
LIST OF TABLES .................................................................................................................................................................... 7
LIST OF FIGURES ................................................................................................................................................................... 8
FEATURES ............................................................................................................................................................................. 10
APPLICATIONS...................................................................................................................................................................... 11
DESCRIPTION........................................................................................................................................................................ 11
BLOCK DIAGRAM ................................................................................................................................................................. 12
1 PIN ASSIGNMENT .......................................................................................................................................................... 13
2 PIN DESCRIPTION ......................................................................................................................................................... 18
3 FUNCTIONAL DESCRIPTION ........................................................................................................................................ 29
3.1 T1 / E1 / J1 MODE SELECTION .............................................................................................................................. 29
3.2 RECEIVE PATH ....................................................................................................................................................... 29
3.2.1 Rx Termination ............................................................................................................................................ 29
3.2.1.1 Receive Differential Mode ........................................................................................................... 29
3.2.1.2 Receive Single Ended Mode ....................................................................................................... 31
3.2.2 Equalizer ..................................................................................................................................................... 32
3.2.2.1 Line Monitor ................................................................................................................................ 32
3.2.2.2 Receive Sensitivity ...................................................................................................................... 32
3.2.3 Slicer ........................................................................................................................................................... 33
3.2.4 Rx Clock & Data Recovery ......................................................................................................................... 33
3.2.5 Decoder ...................................................................................................................................................... 33
3.2.6 Receive System Interface ........................................................................................................................... 33
3.2.7 Receiver Power Down ................................................................................................................................ 34
3.3 TRANSMIT PATH .................................................................................................................................................... 34
3.3.1 Transmit System Interface .......................................................................................................................... 34
3.3.2 Tx Clock Recovery ...................................................................................................................................... 35
3.3.3 Encoder ....................................................................................................................................................... 35
3.3.4 Waveform Shaper ....................................................................................................................................... 35
3.3.4.1 Preset Waveform Template ........................................................................................................ 35
3.3.4.2 User-Programmable Arbitrary Waveform .................................................................................... 37
3.3.5 Line Driver ................................................................................................................................................... 39
3.3.5.1 Transmit Over Current Protection ............................................................................................... 39
3.3.6 Tx Termination ............................................................................................................................................ 39
3.3.6.1 Transmit Differential Mode .......................................................................................................... 39
3.3.6.2 Transmit Single Ended Mode ...................................................................................................... 40
3.3.7 Transmitter Power Down ............................................................................................................................ 41
3.3.8 Output High-Z on TTIP and TRING ............................................................................................................ 41
3.4 JITTER ATTENUATOR (RJA & TJA) ....................................................................................................................... 42
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February 6, 2009
IDT82P2828
28(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
3.5 DIAGNOSTIC FACILITIES .......................................................................................................................................
3.5.1 Bipolar Violation (BPV) / Code Violation (CV) Detection and BPV Insertion ..............................................
3.5.1.1 Bipolar Violation (BPV) / Code Violation (CV) Detection .............................................................
3.5.1.2 Bipolar Violation (BPV) Insertion .................................................................................................
3.5.2 Excessive Zeroes (EXZ) Detection .............................................................................................................
3.5.3 Loss of Signal (LOS) Detection ...................................................................................................................
3.5.3.1 Line LOS (LLOS) .........................................................................................................................
3.5.3.2 System LOS (SLOS) ...................................................................................................................
3.5.3.3 Transmit LOS (TLOS) .................................................................................................................
3.5.4 Alarm Indication Signal (AIS) Detection and Generation ............................................................................
3.5.4.1 Alarm Indication Signal (AIS) Detection ......................................................................................
3.5.4.2 (Alarm Indication Signal) AIS Generation ...................................................................................
3.5.5 PRBS, QRSS, ARB and IB Pattern Generation and Detection ...................................................................
3.5.5.1 Pattern Generation ......................................................................................................................
3.5.5.2 Pattern Detection ........................................................................................................................
3.5.6 Error Counter ..............................................................................................................................................
3.5.6.1 Automatic Error Counter Updating ..............................................................................................
3.5.6.2 Manual Error Counter Updating ..................................................................................................
3.5.7 Receive /Transmit Multiplex Function (RMF / TMF) Indication ...................................................................
3.5.7.1 RMFn Indication ..........................................................................................................................
3.5.7.2 TMFn Indication ..........................................................................................................................
3.5.8 Loopback ....................................................................................................................................................
3.5.8.1 Analog Loopback ........................................................................................................................
3.5.8.2 Remote Loopback .......................................................................................................................
3.5.8.3 Digital Loopback ..........................................................................................................................
3.5.8.4 Dual Loopback ............................................................................................................................
3.5.9 Channel 0 Monitoring ..................................................................................................................................
3.5.9.1 G.772 Monitoring .........................................................................................................................
3.5.9.2 Jitter Measurement (JM) .............................................................................................................
3.6 CLOCK INPUTS AND OUTPUTS ............................................................................................................................
3.6.1 Free Running Clock Outputs on CLKT1/CLKE1 .........................................................................................
3.6.2 Clock Outputs on REFA/REFB ...................................................................................................................
3.6.2.1 REFA/REFB in Clock Recovery Mode ........................................................................................
3.6.2.2 Frequency Synthesizer for REFA Clock Output ..........................................................................
3.6.2.3 Free Run Mode for REFA Clock Output ......................................................................................
3.6.2.4 REFA/REFB Driven by External CLKA/CLKB Input ....................................................................
3.6.2.5 REFA and REFB in Loss of Signal (LOS) or Loss of Clock Condition ........................................
3.6.2.6 Cascading Recovered Clocks of Multiple Devices ......................................................................
3.6.3 MCLK, Master Clock Input ..........................................................................................................................
3.6.4 XCLK, Internal Reference Clock Input ........................................................................................................
3.7 INTERRUPT SUMMARY .........................................................................................................................................
4 MISCELLANEOUS ..........................................................................................................................................................
4.1 RESET .....................................................................................................................................................................
4.1.1 Power-On Reset .........................................................................................................................................
4.1.2 Hardware Reset ..........................................................................................................................................
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28(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
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4.1.3 Global Software Reset ................................................................................................................................ 71
4.1.4 Per-Channel Software Reset ...................................................................................................................... 71
4.2 MICROPROCESSOR INTERFACE ......................................................................................................................... 71
4.3 POWER UP .............................................................................................................................................................. 72
4.4 HITLESS PROTECTION SWITCHING (HPS) SUMMARY ...................................................................................... 72
PROGRAMMING INFORMATION ................................................................................................................................... 75
5.1 REGISTER MAP ...................................................................................................................................................... 75
5.1.1 Global Register ........................................................................................................................................... 75
5.1.2 Per-Channel Register ................................................................................................................................. 76
5.2 REGISTER DESCRIPTION ..................................................................................................................................... 79
5.2.1 Global Register ........................................................................................................................................... 79
5.2.2 Per-Channel Register ................................................................................................................................. 88
JTAG ............................................................................................................................................................................. 121
6.1 JTAG INSTRUCTION REGISTER (IR) .................................................................................................................. 121
6.2 JTAG DATA REGISTER ........................................................................................................................................ 121
6.2.1 Device Identification Register (IDR) .......................................................................................................... 121
6.2.2 Bypass Register (BYP) ............................................................................................................................. 121
6.2.3 Boundary Scan Register (BSR) ................................................................................................................ 121
6.3 TEST ACCESS PORT (TAP) CONTROLLER ....................................................................................................... 121
THERMAL MANAGEMENT .......................................................................................................................................... 123
7.1 JUNCTION TEMPERATURE ................................................................................................................................. 123
7.2 EXAMPLE OF JUNCTION TEMPERATURE CALCULATION ............................................................................... 123
7.3 HEATSINK EVALUATION ..................................................................................................................................... 123
PHYSICAL AND ELECTRICAL SPECIFICATIONS ..................................................................................................... 124
8.1 ABSOLUTE MAXIMUM RATINGS ......................................................................................................................... 124
8.2 RECOMMENDED OPERATING CONDITIONS .................................................................................................... 125
8.3 DEVICE POWER CONSUMPTION AND DISSIPATION (TYPICAL) 1 ................................................................. 126
8.4 DEVICE POWER CONSUMPTION AND DISSIPATION (MAXIMUM) 1 ............................................................... 127
8.5 D.C. CHARACTERISTICS ..................................................................................................................................... 128
8.6 E1 RECEIVER ELECTRICAL CHARACTERISTICS ............................................................................................. 129
8.7 T1/J1 RECEIVER ELECTRICAL CHARACTERISTICS ......................................................................................... 130
8.8 E1 TRANSMITTER ELECTRICAL CHARACTERISTICS ...................................................................................... 131
8.9 T1/J1 TRANSMITTER ELECTRICAL CHARACTERISTICS ................................................................................. 132
8.10 TRANSMITTER AND RECEIVER TIMING CHARACTERISTICS ......................................................................... 133
8.11 CLKE1 TIMING CHARACTERISTICS ................................................................................................................... 135
8.12 JITTER ATTENUATION CHARACTERISTICS ...................................................................................................... 136
8.13 MICROPROCESSOR INTERFACE TIMING ......................................................................................................... 139
8.13.1 Serial Microprocessor Interface ................................................................................................................ 139
8.13.2 Parallel Motorola Non-Multiplexed Microprocessor Interface ................................................................... 141
8.13.2.1 Read Cycle Specification .......................................................................................................... 141
8.13.2.2 Write Cycle Specification .......................................................................................................... 142
8.13.3 Parallel Intel Non-Multiplexed Microprocessor Interface ........................................................................... 143
8.13.3.1 Read Cycle Specification .......................................................................................................... 143
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