PTN5150
CC logic for USB Type-C applications
Rev. 1 — 9 December 2016
Product data sheet
1. General description
PTN5150 is a small thin low power CC Logic chip supporting the USB Type-C connector
application with Configuration Channel (CC) control logic detection and indication
functions. The features of PTN5150 enable USB Type-C connector to be used in both
host and device ends of the Type-C cable. It can support Type-C to USB legacy cables
and adapters defined in USB Type-C Spec. PTN5150 can work autonomously, or can
connect to a controller through I
2
C-bus interface.
PTN5150 can be configured to dual role, host, or device mode through external
configuration pin or through I2C interface. The CC control logic detection and indication
block supports 3 current modes (default current 500 mA/900 mA, medium current 1.5 A
and high current 3.0 A) in DFP advertisement's perspective. When in UFP
advertisement's perspective, the control logic will detect if a DFP with different pull-up Rp
current source is connected. In addition, it will detect if Ra is present on CC1/CC2 pins.
Upon detection of plug orientation, pin ID will indicate if PTN5150 is working under either
host role or device role, and other status will also be reflected in I2C registers.
2. Features and benefits
Support type C connector with existing chipsets
USB Type-C Rev 1.1 compliance
Compatible with legacy OTG hardware and software
Support plug, orientation, role and charging current detection.
USB-ID pin for OTG application
I
2
C-bus interface support for fast mode
CC control logic detection and indication
PORT input pin to configure in DRP (Hi-Z), UFP (low) or DFP (high)
Current mode detection when PTN5150 is operating under UFP (device) role:
default current mode (<0.5 A/0.9 A); medium current mode (<1.5 A); high current
mode (<3.0 A)
Integrated accurate Rp current sources to support default mode and high current
mode under host mode: default current mode at 80
A;
medium current mode at
180
A;
high current mode at 330
A
Integrate Rd resistor in UFP mode
Report detail port states and accessory modes in I2C registers
Support VCONN1/2 power detected status through VCONN Status I2C register
0AH
Current consumption:
Hibernation mode: 4.5
A
Standby in DRP mode: 15
A
NXP Semiconductors
PTN5150
CC logic for USB Type-C applications
Standby in DFP mode: 15
A
Standby in UFP mode: 15
A
Power supply: VDD = 2.7 V to 5.5 V
VBUS_DET: 28 V Absolute Max Tolerance
High ESD protection for VBUS and CC1/2 pins
ESD protection exceeds 7000 V HBM per JDS-001-2012 and 500 V CDM per
JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
Operating Temperature Range:
40 C
to +85
C
X2QFN12 package 1.6 mm
1.6 mm
0.35 mm, 0.4 mm pitch
3. Applications
Tablets/Mobile Devices
Ultrabook/Notebook Computers
Docking Stations
4. Ordering information
Table 1.
Ordering information
Topside
marking
50
Package
Name
X2QFN12
Description
Version
Plastic, super thin quad flat package; no leads; 12 terminals; SOT1355-1
body 1.6 mm
1.6 mm
0.35 mm, 0.4 mm lead pitch.
Type number
PTN5150HX
4.1 Ordering options
Table 2.
Ordering options
Orderable
part number
PTN5150HXMP
Package
X2QFN12
Packing method
Minimum
order quantity
Temperature
T
amb
=
40 C
to +85
C
Type number
PTN5150HX
REEL 13" Q2/T3
10000
*STANDARD MARK
SMD DP
PTN5150
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 9 December 2016
2 of 28
NXP Semiconductors
PTN5150
CC logic for USB Type-C applications
5. Functional diagram
VBUS_DET
Rp
ID
ADR/CON_DET
ENB
CC LEVEL
DETECTION
AND INDICATION
VDD
Rd
Rp
CC1
VDD
PORT
ROLE
(UFP/DFP/DRP)
CONTROL
CC2
Rd
DEVICE CONTROL AND MANAGEMENT
SDA/OUT1
SCL/OUT2
INTB/OUT3
aaa-019339
Fig 1.
Functional diagram
6. Pinning information
6.1 Pinning
terminal 1
index area
CC1 1
10 GND
ADR/CON_DET 5
12 VDD
11 ENB
PTN5150
CC2 2
PORT 3
VBUS_DET 4
7 SDA/OUT1
INTB/OUT3 6
aaa-019340
Transparent top view
Fig 2.
Pin configuration
PTN5150
All information provided in this document is subject to legal disclaimers.
9 ID
8 SCL/OUT2
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 9 December 2016
3 of 28
NXP Semiconductors
PTN5150
CC logic for USB Type-C applications
6.2 Pin description
Table 3.
Symbol
1
2
3
Pin description
Pin
CC1
CC2
PORT
Input
Trinary GPIO Input selection run from VDD
PORT= VDD: DFP mode (Rp = 80uA power default for non-I2C mode).
PORT= Mid (or floating): DRP mode
PORT=GND: UFP mode
If ADR = High or Low (I2C mode), PORT input status will be only latched during
power up. To change the mode selection, system must write I2C register bit to
override mode selection.
If ADR = Mid (no- I2C mode). PORT input can be dynamically change.
4
5
VBUS_DET
Input
VBUS Detection Pin. (28 V Max Tolerance)
Directly tie to VBUS of the USB Type-C receptacle
ADR/CON_DET I/O
Trinary GPIO Input ADR pin run from VDD
Type
I/O
Description
Configure Channels as defined in USB Type-C specification
•
•
•
•
•
6
INTB/OUT3
O/D
output
ADR pull up to VDD with 10 k resistor (I2C Enabled with ADDR bit 6 equal to
1, I2C Address 0x7A)
ADR pull down to GND with 10 k resistor. (I2C Enabled with ADDR bit 6
equal to 0, I2C Address 0x3A)
ADR = Mid or floating (Pin 6/7/8) configured as OUT1/2/3 in non-I2C mode
Output. This pin will automatically switch from input to CON_DET output in
"non-I2C mode or set 09H bit[0] to 0" after TINPUTLATCH
CON_DET = High (Connection Detected)
CON_DET = Low (No Connection)
Interrupt to notify I2C status register changed
INTB: (only valid in I2C mode)
•
•
•
•
7
SDA/OUT1
O/D
Input
/output
Low = Interrupt asserted
Hi-Z = Interrupt de-asserted
Low = Analog Audio Detected
Hi-Z = No Detection
OUT3: (only valid in non- I2C mode)
I2C SDA (Open Drain Input & Output)
OUT 2 & OUT 1 : (Open Drain Output)
0
1
1
0
0
1
= high current mode
= medium current mode
= default current mode
8
SCL/OUT2
O/D
Input
/output
I2C SCL (Open Drain Input)
OUT 2 & OUT 1 : (Open Drain Output)
0
1
1
0
0
1
= high current mode
= medium current mode
= default current mode
9
ID
O/D
output
ID (Open Drain Output)
Low = DFP mode detected valid UFP on CC1 or CC2 line. This signal is used to
enable OTG mode, requires external pull up resistor.
PTN5150
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1 — 9 December 2016
4 of 28
NXP Semiconductors
PTN5150
CC logic for USB Type-C applications
Table 3.
Symbol
10
11
Pin description
…continued
Pin
GND
ENB
Type
Power
Input
Description
Ground
Chip Enable and Disable
•
•
12
VDD
Power
Low = Chip Enable
High = Chip Disable to Hiberation mode. Note that I2C register values are lost
when ENB is HIGH.
Power supply
7. Functional description
7.1 CC detection and indication block
For USB Type-C solution, two pins on the connector, CC1 and CC2, are used to establish
and manage the DFP/UFP connection between a host port and a device port.
A hardware GPIO trinary pin, PORT, is provided to configure PTN5150 in either
DFP/DRP/UFP mode alternatively, the PORT input can be override later by override the
I2C registers. If the GPIO Trinary ADR input is mid-level or floating (non I2C), PORT input
pin can dynamically change at any time to reconfigure the DFP/DRP/UFP. The GPIO
trinary input pins should be powered by VDD.
•
When PTN5150 is operating under host role, different current modes
(high/medium/default) can be configured through I2C register. During initial power up,
default current mode is being selected. In order to indicate different current modes,
three Rp current sources are being implemented.
Table 4.
Current source implementation for each DFP advertisement
Current source to VDD
80
A
180
A
330
A
Current source precision
20
%
8
%
8
%
DFP advertisement
Default USB Power
1.5 A at 5 V
3.0 A at 5 V
Internal comparators are constantly monitoring the voltage levels of CC1 and CC2 pins.
PTN5150 reports if an UFP (device) or powered cable is connected externally on the CC
pins. When no external connection is detected, cable connected bit in the I2C register will
be cleared. Any changes in the attach/detach events or Rp current source changes will
trigger INTB pin to go LOW.
Table 5.
UFP mode
Table 6.
RD implementation for each UFP advertisement
RD value
5.1 k
RD accuracy
10
%
UFP advertisement
Voltage range detection for each DFP advertisement
UFP (V
Rd
) voltage
range
0.25 V to 1.50 V
0.45 V to 1.50 V
0.85 V to 2.45 V
Powered cable/adapter No connect (V
open)
V
Ra
voltage range
voltage range
0.00 V to 0.15 V
0.00 V to 0.35 V
0.00 V to 0.75 V
>1.65 V
>1.65 V
>2.75 V
© NXP Semiconductors N.V. 2016. All rights reserved.
DFP advertisement
Default USB Power
1.5 A at 5 V
3.0 A at 5 V
PTN5150
All information provided in this document is subject to legal disclaimers.
Product data sheet
Rev. 1 — 9 December 2016
5 of 28
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