74AXP1T57
Rev. 5 — 3 July 2017
Dual supply configurable multiple function gate
Product data sheet
1
General description
The 74AXP1T57 is a dual supply configurable multiple function gate with Schmitt-trigger
inputs. It features three inputs (A, B and C), an output (Y) and dual supply pins (V
CCI
and
V
CCO
). The inputs are referenced to V
CCI
and the output is referenced to V
CCO
. All inputs
can be connected directly to V
CCI
or GND. V
CCI
can be supplied at any voltage between
0.7 V and 2.75 V and V
CCO
can be supplied at any voltage between 1.2 V and 5.5 V. This
feature allows voltage level translation. The 74AXP1T57 can be configured as any of the
following logic functions AND, OR, NAND, NOR, XNOR, inverter and buffer.
This device ensures very low static and dynamic power consumption across the entire
supply range and is fully specified for partial power down applications using I
OFF
. The
I
OFF
circuitry disables the output, preventing the potentially damaging backflow current
through the device when it is powered down.
2
Features and benefits
•
Wide supply voltage range:
–
V
CCI
: 0.7 V to 2.75 V
–
V
CCO
: 1.2 V to 5.5 V
•
Low input capacitance; C
I
= 0.6 pF (typical)
•
Low output capacitance; C
O
= 1.8 pF (typical)
•
Low dynamic power consumption; C
PD
= 0.6 pF at V
CCI
= 1.2 V (typical)
•
Low dynamic power consumption; C
PD
= 7.1 pF at V
CCO
= 3.3 V (typical)
•
Low static power consumption; I
CCI
= 0.5 μA (85 °C maximum)
•
Low static power consumption; I
CCO
= 1.8 μA (85 °C maximum)
•
High noise immunity
•
Complies with JEDEC standard:
–
JESD8-12A.01 (1.1 V to 1.3 V; A, B, C inputs)
–
JESD8-11A.01 (1.4 V to 1.6 V)
–
JESD8-7A (1.65 V to 1.95 V)
–
JESD8-5A.01 (2.3 V to 2.7 V)
–
JESD8-C (2.7 V to 3.6 V; Y output)
–
JESD12-6 (4.5 V to 5.5 V; Y output)
•
ESD protection:
–
HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2 kV
–
CDM JESD22-C101E exceeds 1000 V
•
Latch-up performance exceeds 100 mA per JESD78D Class II
•
Inputs accept voltages up to 2.75 V
•
Low noise overshoot and undershoot < 10 % of V
CCO
•
I
OFF
circuitry provides partial power-down mode operation
•
Multiple package options
Nexperia
Dual supply configurable multiple function gate
•
Specified from -40 °C to +85 °C
74AXP1T57
3
Ordering information
Package
Temperature
range
Name
Description
Version
SOT765-1
SOT833-1
SOT1116
SOT1203
Table 1. Ordering information
Type number
74AXP1T57DC
74AXP1T57GT
74AXP1T57GN
74AXP1T57GS
74AXP1T57GX
-40 °C to +85 °C
-40 °C to +85 °C
-40 °C to +85 °C
-40 °C to +85 °C
-40 °C to +85 °C
VSSOP8 plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
XSON8
XSON8
XSON8
plastic extremely thin small outline package; no leads;
8 terminals; body 1 x 1.95 x 0.5 mm
extremely thin small outline package; no leads;
8 terminals; body 1.2 x 1.0 x 0.35 mm
extremely thin small outline package; no leads;
8 terminals; body 1.35 x 1.0 x 0.35 mm
X2SON8 plastic thermal enhanced extremely thin small outline
SOT1233
package; no leads; 8 terminals; body 1.35 x 0.8 x 0.35 mm
4
Marking
Marking code
rD
rD
rD
rD
rD
[1]
Table 2. Marking
Type number
74AXP1T57DC
74AXP1T57GT
74AXP1T57GN
74AXP1T57GS
74AXP1T57GX
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5
Functional diagram
A
2
6
Y
A
2
6
Y
B
3
B
3
C
7
V
CCI
V
CCO
aaa-018526
C
7
aaa-018525
Figure 1. Logic symbol
Figure 2. Logic diagram
74AXP1T57
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 5 — 3 July 2017
2 / 24
Nexperia
Dual supply configurable multiple function gate
74AXP1T57
6
Pinning information
6.1 Pinning
74AXP1T57
V
CCI
1
8
V
CCO
74AXP1T57
V
CCI
1
8
V
CCO
A
2
4
GND
B
3
5
aaa-027036
74AXP1T57
V
CCI
1
A 2
B 3
GND 4
8 V
CCO
7 C
6 Y
5 GND
A
2
7
C
7
C
B
3
6
Y
6
Y
GND
4
5
GND
GND
Transparent top view
aaa-018527
aaa-018528
Transparent top view
Figure 3. Pin configuration VSSOP8 Figure 4. Pin configuration XSON8
Figure 5. Pin configuration X2SON8
6.2 Pin description
Table 3. Pin description
Symbol
V
CCI
A, B, C
GND
Y
V
CCO
[1]
[1]
Pin
1
2, 3, 7
4, 5
6
8
Description
input supply voltage
data input
ground (0 V)
data output
output supply voltage
All GND pins must be connected to ground (0 V).
74AXP1T57
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 5 — 3 July 2017
3 / 24
Nexperia
Dual supply configurable multiple function gate
74AXP1T57
7
Functional description
Table 4. Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
Supply voltage
V
CCI
0.7 V to 2.75 V
0.7 V to 2.75 V
0.7 V to 2.75 V
0.7 V to 2.75 V
0.7 V to 2.75 V
0.7 V to 2.75 V
0.7 V to 2.75 V
0.7 V to 2.75 V
GND
0.7 V to 2.75 V
GND
Input
V
CCO
1.2 V to 5.5 V
1.2 V to 5.5 V
1.2 V to 5.5 V
1.2 V to 5.5 V
1.2 V to 5.5 V
1.2 V to 5.5 V
1.2 V to 5.5 V
1.2 V to 5.5 V
1.2 V to 5.5 V
GND
GND
Output
B
L
L
H
H
L
L
H
H
X
X
X
C
L
L
L
L
H
H
H
H
X
X
X
A
L
H
L
H
L
H
L
H
X
X
X
Y
H
L
H
L
L
L
H
H
Z
Z
Z
7.1 Logic configurations
Table 5. Function selection table
Logic function
2-input AND
2-input AND with both inputs inverted
2-input NAND with inverted input
2-input OR with inverted input
2-input NOR
2-input NOR with both inputs inverted
2-input XNOR
Inverter
Buffer
Figure
see
Figure 6
see
Figure 9
see
Figure 7
and
Figure 8
see
Figure 7
and
Figure 8
see
Figure 9
see
Figure 6
see
Figure 10
see
Figure 11
see
Figure 12
74AXP1T57
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 5 — 3 July 2017
4 / 24
Nexperia
Dual supply configurable multiple function gate
V
CCI
B
C
B
C
1
2
B
Y
3
4
8
7
6
5
C
Y
V
CCO
B
C
B
C
74AXP1T57
V
CCO
1
2
8
7
6
5
C
Y
V
CCI
Y
Y
B
Y
3
4
aaa-018530
aaa-018531
Figure 6. 2-input AND gate or 2-input NOR gate with
both inputs inverted
V
CCI
A
C
A
C
1
A
2
3
Y
4
8
7
6
5
C
Y
V
CCO
Figure 7. 2-input NAND gate with input B inverted or 2-
input OR gate with inverted C input
V
CCI
A
C
A
C
1
A
2
3
Y
4
8
7
6
5
C
Y
V
CCO
Y
Y
aaa-018532
aaa-018533
Figure 8. 2-input NAND gate with input C inverted or 2-
input OR gate with inverted A input
V
CCI
1
B
C
Y
2
B
3
4
8
7
6
5
C
Y
V
CCO
Figure 9. 2-input NOR gate or 2-input AND gate with
both inputs inverted
V
CCI
1
A
Y
A
2
3
4
8
7
6
5
Y
V
CCO
aaa-018534
aaa-018535
Figure 10. 2-input XNOR gate
V
CCI
Figure 11. Inverter
V
CCO
1
B
Y
2
B
3
4
8
7
6
5
Y
aaa-018536
Figure 12. Buffer
74AXP1T57
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 5 — 3 July 2017
5 / 24
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