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74LCX00 — Low Voltage Quad 2-Input NAND Gate with 5V Tolerant Inputs
December 2013
74LCX00
Low Voltage Quad 2-Input NAND Gate
with 5V Tolerant Inputs
Features
■
5V tolerant inputs
■
2.3V–3.6V V
CC
specifications provided
■
5.2ns t
PD
max. (V
CC
=
3.3V), 10µA I
CC
max.
■
Power down high impedance inputs and outputs
■
±24mA output drive (V
CC
=
3.0V)
■
Implements
proprietary
noise/EMI reduction circuitry
■
Latch-up performance exceeds JEDEC 78 conditions
■
ESD performance:
General Description
The LCX00 contains four 2-input NAND gates. The
inputs tolerate voltages up to 7V allowing the interface of
5V systems to 3V systems.
The 74LCX00 is fabricated with advanced CMOS tech-
nology to achieve high speed operation while maintain-
ing CMOS low power dissipation.
– Human body model
>
2000V
– Machine model
>
200V
■
Leadless DQFN package
Ordering Information
Order Number
74LCX00M
74LCX00SJ
74LCX00BQX
(1)
74LCX00MTC
Package
Number
M14A
M14D
MLP14A
MTC14
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC
MO-241, 2.5 x 3.0mm
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Note:
1. DQFN package available in Tape and Reel only.
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
unsigned int i;signed int j1=0,j0=0; // // The FPU should be enabled because some compilers will use floating- // point registers, even for non-floating-point code. If the FPU is n ......
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