TSM4NC50CP
Taiwan Semiconductor
N-Channel Power MOSFET
500V, 4A, 2.7Ω
FEATURES
● 100% UIS and R
g
tested
● Advanced planar process
● Compliant to RoHS Directive 2011/65/EU and in
accordance to WEEE 2002/96/EC
● Halogen-free according to IEC 61249-2-21
KEY PERFORMANCE PARAMETERS
PARAMETER
V
DS
R
DS(on)
(max)
Q
g
VALUE
500
2.7
12
UNIT
V
Ω
nC
APPLICATIONS
● AC/DC LED Lighting
● Power Supply
● Charger
TO-252 (DPAK)
Notes:
MSL 3 (Moisture Sensitivity Level) per J-STD-020
ABSOLUTE MAXIMUM RATINGS
(T
A
= 25°C unless otherwise noted)
PARAMETER
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current
Pulsed Drain Current
(Note 1)
SYMBOL
V
DS
V
GS
T
C
= 25°C
T
C
= 100°C
I
D
I
DM
P
DTOT
E
AS
I
AS
T
J
, T
STG
(Note 3)
(Note 3)
Limit
500
±20
4
2.5
16
83
78.4
2.8
- 55 to +150
UNIT
V
V
A
A
W
mJ
A
°C
(Note 2)
Total Power Dissipation @ T
C
= 25°C
Single Pulse Avalanche Energy
Single Pulse Avalanche Current
Operating Junction and Storage Temperature Range
THERMAL PERFORMANCE
PARAMETER
Junction to Case Thermal Resistance
Junction to Ambient Thermal Resistance
SYMBOL
R
ӨJC
R
ӨJA
Limit
1.5
62
UNIT
°C/W
°C/W
Thermal Performance Note:
R
ӨJA
is the sum of the junction-to-case and case-to-ambient thermal resistances. The case-
thermal reference is defined at the solder mounting surface of the drain pins. R
ӨJA
is guaranteed by design while R
ӨCA
is
determined by the user’s board design. R
ӨJA
shown below for single device operation on FR-4 PCB in still air.
1
Version: A1609
TSM4NC50CP
Taiwan Semiconductor
ELECTRICAL SPECIFICATIONS
(T
A
= 25°C unless otherwise noted)
PARAMETER
Static
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate Body Leakage
Zero Gate Voltage Drain Current
Drain-Source On-State Resistance
(Note 4)
CONDITIONS
V
GS
= 0V, I
D
= 250µA
V
DS
= V
GS
, I
D
= 250µA
V
GS
= ±20V, V
DS
= 0V
V
DS
= 500V, V
GS
= 0V
V
GS
= 10V, I
D
=1.7A
SYMBOL
BV
DSS
V
GS(TH)
I
GSS
I
DSS
R
DS(on)
MIN
500
2
--
--
--
TYP
--
2.2
--
--
2.4
MAX
--
3
±100
1
2.7
UNIT
V
V
nA
µA
Ω
Dynamic
(Note 5)
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
Switching
(Note 6)
Q
g
V
DS
= 400V, I
D
= 3.4A,
V
GS
= 10V
Q
gs
Q
gd
C
iss
V
DS
= 50V, V
GS
= 0V,
f = 1.0MHz
f = 1.0MHz
C
oss
C
rss
R
g
--
--
--
--
--
--
--
12
2.2
4.4
453
27
1
2.6
--
--
--
--
--
--
5.2
Ω
pF
nC
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
Source-Drain Diode
Forward Voltage
(Note 4)
t
d(on)
V
DD
= 250V, R
G
= 5Ω,
I
D
= 3.4A, V
GS
= 10V
t
r
t
d(off)
t
f
--
--
--
--
5.4
18.4
12.4
19.6
--
--
--
--
ns
I
S
= 3.4A, V
GS
= 0V
I
S
= 3.4A
dI
F
/dt = 100A/μs
V
SD
t
rr
Q
rr
--
--
--
--
233
0.84
1.3
--
--
V
ns
μC
Reverse Recovery Time
Reverse Recovery Charge
Notes:
1.
2.
3.
4.
5.
6.
Current limited by package
Pulse width limited by the maximum junction temperature
L = 20mH, I
AS
= 2.8A, V
DD
= 50V, R
G
= 25Ω, Starting T
J
= 25 C
Pulse test: PW ≤ 300µs, duty cycle ≤ 2%
For DESIGN AID ONLY, not subject to production testing.
Switching time is essentially independent of operating temperature.
o
ORDERING INFORMATION
PART NO.
TSM4NC50CP ROG
PACKAGE
TO-252 (DPAK)
PACKING
2,500pcs / 13” Reel
2
Version: A1609
TSM4NC50CP
Taiwan Semiconductor
CHARACTERISTICS CURVES
(T
A
= 25°C unless otherwise noted)
Output Characteristics
4
V
GS
=10V
V
GS
=9V
V
GS
=8V
V
GS
=7V
V
GS
=6V
V
GS
=5V
V
GS
=4V
4
Transfer Characteristics
I
D
, Drain Current (A)
3
I
D
, Drain Current (A)
3
2
2
25℃
-55℃
1
150℃
1
0
0
2
4
6
8
10
12
14
0
0
2
4
6
8
V
DS
, Drain to Source Voltage (V)
V
GS
, Gate to Source Voltage (V)
Gate-Source Voltage vs. Gate Charge
10
R
DS(ON)
, Drain-Source On-Resistance (Ω)
On-Resistance vs. Drain Current
4
3.5
3
2.5
2
1.5
1
0.5
0
0
0.5
1
1.5
2
2.5
3
3.5
4
V
GS
=10V
V
GS
, Gate to Source Voltage (V)
8
V
DS
=400V
I
D
=3.4A
6
4
2
0
0
3
6
9
12
15
I
D
, Drain Current (A)
On-Resistance vs. Junction Temperature
Q
g
, Gate Charge (nC)
On-Resistance vs. Gate-Source Voltage
R
DS(on)
, Drain-Source On-Resistance (Ω)
3
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2
4
5
6
7
8
9
10
I
D
=1.7A
R
DS(on)
, Drain-Source On-Resistance
(Normalized)
3
2.5
2
1.5
1
0.5
0
-75
-50
-25
0
25
50
75
100 125 150
V
GS
=10V
I
D
=1.7A
T
J
, Junction Temperature (°C)
V
GS
, Gate to Source Voltage (V)
3
Version: A1609
TSM4NC50CP
Taiwan Semiconductor
CHARACTERISTICS CURVES
(T
A
= 25°C unless otherwise noted)
Capacitance vs. Drain-Source Voltage
BV
DSS
(Normalized)
Drain-Source Breakdown Voltage
800
700
1.2
I
D
=1mA
1.1
BV
DSS
vs. Junction Temperature
C, Capacitance (pF)
600
500
400
300
200
100
CRSS
0
0.1
1
10
100
1000
COSS
CISS
1
0.9
0.8
-75
-50
-25
0
25
50
75
100 125 150
V
DS
, Drain to Source Voltage (V)
Maximum Safe Operating Area, Junction-to-Case
20
10
100
T
J
, Junction Temperature (°C)
Source-Drain Diode Forward Current vs. Voltage
I
S
, Reverse Drain Current (A)
I
D
, Drain Current (A)
R
DS(ON)
10
1
150℃
1
25℃
SINGLE PULSE
R
ӨJC
=1.5°C/W
T
C
=25°C
0.1
1
10
100
1000
0.1
0.2
0.4
0.6
0.8
-55℃
1
1.2
V
DS
, Drain to Source Voltage (V)
10
V
SD
, Body Diode Forward Voltage (V)
Normalized Thermal Transient Impedance, Junction-to-Case
Normalized Effective Transient
Thermal Impedance, Z
ӨJC
SINGLE PULSE
R
ӨJC
=1.5°C/W
1
0.1
Duty=0.5
Duty=0.2
Duty=0.1
Duty=0.05
Duty=0.02
Duty=0.01
Single
0.001
0.01
Notes:
Duty = t
1
/ t
2
T
J
= T
C
+ P
DM
x Z
ӨJC
x R
ӨJC
0.1
0.01
0.0001
t, Square Wave Pulse Duration (sec)
4
Version: A1609
TSM4NC50CP
Taiwan Semiconductor
PACKAGE OUTLINE DIMENSIONS
(Unit: Millimeters)
TO-252
SUGGESTED PAD LAYOUT
(Unit: Millimeters)
MARKING DIAGRAM
Y
= Year Code
M
= Month Code
O
=Jan
P
=Feb
S
=May
T
=Jun
W
=Sep
X
=Oct
L
= Lot Code (1~9, A~Z)
4NC50
YML
Q
=Mar
U
=Jul
Y
=Nov
R
=Apr
V
=Aug
Z
=Dec
5
Version: A1609
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